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[RISCV] Fix and refactor Zvk sched classes #86519

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Merged
merged 1 commit into from
Apr 2, 2024
Merged

[RISCV] Fix and refactor Zvk sched classes #86519

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6 changes: 0 additions & 6 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2985,12 +2985,6 @@ multiclass VPseudoVWALU_VV_VX {
}
}

multiclass VPseudoVWALU_VV_VX_VI<Operand ImmType> : VPseudoVWALU_VV_VX {
foreach m = MxListW in {
defm "" : VPseudoBinaryW_VI<ImmType, m>;
}
}

multiclass VPseudoVWMUL_VV_VX {
foreach m = MxListW in {
defvar mx = m.MX;
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57 changes: 22 additions & 35 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
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Original file line number Diff line number Diff line change
Expand Up @@ -269,22 +269,16 @@ multiclass VPseudoBinaryV_S_NoMask_Zvk<LMULInfo m> {
multiclass VPseudoVALU_V_NoMask_Zvk {
foreach m = MxListVF4 in {
defvar mx = m.MX;
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);

defm "" : VPseudoBinaryV_V_NoMask_Zvk<m>,
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx>;
}
}

multiclass VPseudoVALU_S_NoMask_Zvk {
foreach m = MxListVF4 in {
defvar mx = m.MX;
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);

defm "" : VPseudoBinaryV_S_NoMask_Zvk<m>,
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx>;
}
}

Expand All @@ -294,59 +288,46 @@ multiclass VPseudoVALU_V_S_NoMask_Zvk
multiclass VPseudoVALU_VV_NoMask_Zvk {
foreach m = MxListVF4 in {
defvar mx = m.MX;
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);

defm _VV : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, m.vrclass, m>,
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
SchedTernary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", "ReadVIALUV", mx>;
}
}

multiclass VPseudoVALU_VI_NoMask_Zvk {
foreach m = MxListVF4 in {
defvar mx = m.MX;
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);

defm _VI : VPseudoTernaryNoMask_Zvk<m.vrclass, m.vrclass, uimm5, m>,
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
SchedTernary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", "ReadVIALUV", mx>;
}
}

multiclass VPseudoVALU_VI_NoMaskTU_Zvk {
foreach m = MxListVF4 in {
defvar mx = m.MX;
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);

defm _VI : VPseudoBinaryNoMaskTU_Zvk<m.vrclass, m.vrclass, uimm5, m>,
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
forceMergeOpRead=true>;
}
}

multiclass VPseudoVALU_VV_NoMaskTU_Zvk {
foreach m = MxListVF4 in {
defvar mx = m.MX;
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);

defm _VV : VPseudoBinaryNoMaskTU_Zvk<m.vrclass, m.vrclass, m.vrclass, m>,
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
forceMergeOpRead=true>;
}
}

multiclass VPseudoVCLMUL_VV_VX {
foreach m = MxList in {
defvar mx = m.MX;
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
defvar WriteVIALUX_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);

defm "" : VPseudoBinaryV_VV<m>,
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
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This is a multiply so shouldn't it use the multiply scheduler class? Really it should have its own class.

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I will address this in a follow up patch, where I plan to make sure that sched classes match with behavior. This patch was about the right number of classes.

forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,
forceMergeOpRead=true>;
}
}

Expand All @@ -362,11 +343,17 @@ multiclass VPseudoUnaryV_V<LMULInfo m> {
multiclass VPseudoVALU_V {
foreach m = MxList in {
defvar mx = m.MX;
defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);

defm "" : VPseudoUnaryV_V<m>,
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
SchedUnary<"WriteVIALUV", "ReadVIALUV", mx,
forceMergeOpRead=true>;
}
}

multiclass VPseudoVWALU_VV_VX_VI<Operand ImmType> : VPseudoVWALU_VV_VX {
foreach m = MxListW in {
defm "" : VPseudoBinaryW_VI<ImmType, m>,
SchedUnary<"WriteVIWALUV", "ReadVIWALUV", m.MX,
forceMergeOpRead=true>;
}
}

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