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[DAGCombiner] Set disjoint flag in add->or and xor->or combines #86925

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Merged
merged 2 commits into from
Mar 28, 2024
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[DAGCombiner] Set disjoint flag in add->or and xor->or combines #86925

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a9fb736
[DAGCombiner] Set disjoint flag in add->or and xor->or combines
lukel97 Mar 28, 2024
92e67fa
Fix Lanai UTC test
lukel97 Mar 28, 2024
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14 changes: 10 additions & 4 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2887,8 +2887,11 @@ SDValue DAGCombiner::visitADD(SDNode *N) {

// fold (a+b) -> (a|b) iff a and b share no bits.
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
DAG.haveNoCommonBitsSet(N0, N1))
return DAG.getNode(ISD::OR, DL, VT, N0, N1);
DAG.haveNoCommonBitsSet(N0, N1)) {
SDNodeFlags Flags;
Flags.setDisjoint(true);
Comment on lines +2891 to +2892
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Side note, we should fix the bad API of SDNodeFlags

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Yeah, this was gnarly but I just tried to follow what we do for nonneg

return DAG.getNode(ISD::OR, DL, VT, N0, N1, Flags);
}

// Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) {
Expand Down Expand Up @@ -9289,8 +9292,11 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {

// fold (a^b) -> (a|b) iff a and b share no bits.
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
DAG.haveNoCommonBitsSet(N0, N1))
return DAG.getNode(ISD::OR, DL, VT, N0, N1);
DAG.haveNoCommonBitsSet(N0, N1)) {
SDNodeFlags Flags;
Flags.setDisjoint(true);
return DAG.getNode(ISD::OR, DL, VT, N0, N1, Flags);
}

// look for 'add-like' folds:
// XOR(N0,MIN_SIGNED_VALUE) == ADD(N0,MIN_SIGNED_VALUE)
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/lanai_isel.ll.expected
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Expand Up @@ -7,7 +7,7 @@ define i64 @i64_test(i64 %i) nounwind readnone {
; CHECK-NEXT: t0: ch,glue = EntryToken
; CHECK-NEXT: t5: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.0)> TargetFrameIndex:i32<-2>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
; CHECK-NEXT: t7: i32 = ADD_I_LO TargetFrameIndex:i32<0>, TargetConstant:i32<0>
; CHECK-NEXT: t29: i32 = OR_I_LO t7, TargetConstant:i32<4>
; CHECK-NEXT: t29: i32 = OR_I_LO disjoint t7, TargetConstant:i32<4>
; CHECK-NEXT: t22: i32,ch = LDW_RI<Mem:(dereferenceable load (s32) from %ir.loc + 4, basealign 8)> t29, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
; CHECK-NEXT: t24: i32 = ADD_R t5, t22, TargetConstant:i32<0>
; CHECK-NEXT: t3: i32,ch = LDW_RI<Mem:(load (s32) from %fixed-stack.1, align 8)> TargetFrameIndex:i32<-1>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
Expand Down Expand Up @@ -52,7 +52,7 @@ define i64 @i16_test(i16 %i) nounwind readnone {
; CHECK-NEXT: t33: i32,ch = CopyFromReg t0, Register:i32 $r0
; CHECK-NEXT: t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33
; CHECK-NEXT: t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0>
; CHECK-NEXT: t21: i32 = OR_I_LO t1, TargetConstant:i32<2>
; CHECK-NEXT: t21: i32 = OR_I_LO disjoint t1, TargetConstant:i32<2>
; CHECK-NEXT: t23: i32,ch = LDHz_RI<Mem:(load (s16) from %fixed-stack.0 + 2, basealign 4)> t21, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
; CHECK-NEXT: t22: i32,ch = LDHz_RI<Mem:(dereferenceable load (s16) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
; CHECK-NEXT: t24: i32 = ADD_R t23, t22, TargetConstant:i32<0>
Expand All @@ -75,7 +75,7 @@ define i64 @i8_test(i8 %i) nounwind readnone {
; CHECK-NEXT: t33: i32,ch = CopyFromReg t0, Register:i32 $r0
; CHECK-NEXT: t14: ch,glue = CopyToReg t0, Register:i32 $rv, t33
; CHECK-NEXT: t1: i32 = ADD_I_LO TargetFrameIndex:i32<-1>, TargetConstant:i32<0>
; CHECK-NEXT: t21: i32 = OR_I_LO t1, TargetConstant:i32<3>
; CHECK-NEXT: t21: i32 = OR_I_LO disjoint t1, TargetConstant:i32<3>
; CHECK-NEXT: t23: i32,ch = LDBz_RI<Mem:(load (s8) from %fixed-stack.0 + 3, basealign 4)> t21, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
; CHECK-NEXT: t22: i32,ch = LDBz_RI<Mem:(dereferenceable load (s8) from %ir.loc)> TargetFrameIndex:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, t0
; CHECK-NEXT: t24: i32 = ADD_R t23, t22, TargetConstant:i32<0>
Expand Down