[RISCV] Generate more W instructons #87237
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@llvm/pr-subscribers-backend-risc-v Author: Pengcheng Wang (wangpc-pp) ChangesWe rename If all the users of an instruction just use the low 32 bits, we can A quick test on Coremark (
Full diff: https://github.com/llvm/llvm-project/pull/87237.diff 5 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6ef2289bb4beeb..537e2cb12aba32 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1226,9 +1226,9 @@ def TuneNoSinkSplatOperands
"false", "Disable sink splat operands to enable .vx, .vf,"
".wx, and .wf instructions">;
-def TuneNoStripWSuffix
- : SubtargetFeature<"no-strip-w-suffix", "EnableStripWSuffix", "false",
- "Disable strip W suffix">;
+def TunePreferWInst
+ : SubtargetFeature<"prefer-w-inst", "PreferWInst", "true",
+ "Prefer instructions with W suffix">;
def TuneConditionalCompressedMoveFusion
: SubtargetFeature<"conditional-cmv-fusion", "HasConditionalCompressedMoveFusion",
diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 39d420c2fbf080..e0f2d531362aee 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -46,6 +46,9 @@ static cl::opt<bool> DisableSExtWRemoval("riscv-disable-sextw-removal",
static cl::opt<bool> DisableStripWSuffix("riscv-disable-strip-w-suffix",
cl::desc("Disable strip W suffix"),
cl::init(false), cl::Hidden);
+static cl::opt<bool> EnableAppendWSuffix("riscv-enable-append-w-suffix",
+ cl::desc("Enable append W suffix"),
+ cl::init(false), cl::Hidden);
namespace {
@@ -60,6 +63,8 @@ class RISCVOptWInstrs : public MachineFunctionPass {
const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
bool stripWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII,
const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
+ bool appendWSuffixes(MachineFunction &MF, const RISCVInstrInfo &TII,
+ const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
@@ -672,9 +677,6 @@ bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
const RISCVInstrInfo &TII,
const RISCVSubtarget &ST,
MachineRegisterInfo &MRI) {
- if (DisableStripWSuffix || !ST.enableStripWSuffix())
- return false;
-
bool MadeChange = false;
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
@@ -698,6 +700,42 @@ bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
return MadeChange;
}
+bool RISCVOptWInstrs::appendWSuffixes(MachineFunction &MF,
+ const RISCVInstrInfo &TII,
+ const RISCVSubtarget &ST,
+ MachineRegisterInfo &MRI) {
+ bool MadeChange = false;
+ for (MachineBasicBlock &MBB : MF) {
+ for (MachineInstr &MI : MBB) {
+ unsigned Opc;
+ // TODO: Add more.
+ switch (MI.getOpcode()) {
+ default:
+ continue;
+ case RISCV::ADD:
+ Opc = RISCV::ADDW;
+ break;
+ case RISCV::ADDI:
+ Opc = RISCV::ADDIW;
+ break;
+ case RISCV::MUL:
+ Opc = RISCV::MULW;
+ break;
+ case RISCV::SLLI:
+ Opc = RISCV::SLLIW;
+ break;
+ }
+
+ if (hasAllWUsers(MI, ST, MRI)) {
+ MI.setDesc(TII.get(Opc));
+ MadeChange = true;
+ }
+ }
+ }
+
+ return MadeChange;
+}
+
bool RISCVOptWInstrs::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
@@ -711,7 +749,12 @@ bool RISCVOptWInstrs::runOnMachineFunction(MachineFunction &MF) {
bool MadeChange = false;
MadeChange |= removeSExtWInstrs(MF, TII, ST, MRI);
- MadeChange |= stripWSuffixes(MF, TII, ST, MRI);
+
+ if (!(DisableStripWSuffix || ST.preferWInst()))
+ MadeChange |= stripWSuffixes(MF, TII, ST, MRI);
+
+ if (EnableAppendWSuffix || ST.preferWInst())
+ MadeChange |= appendWSuffixes(MF, TII, ST, MRI);
return MadeChange;
}
diff --git a/llvm/test/CodeGen/RISCV/prefer-w-inst.ll b/llvm/test/CodeGen/RISCV/prefer-w-inst.ll
new file mode 100644
index 00000000000000..5aebd0fcfe30b7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/prefer-w-inst.ll
@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=NO-PREFER-W-INST %s
+; RUN: llc -mtriple=riscv64 -mattr=+m -riscv-disable-strip-w-suffix -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=NO-STRIP %s
+; RUN: llc -mtriple=riscv64 -mattr=+m,+prefer-w-inst -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=PREFER-W-INST %s
+; RUN: llc -mtriple=riscv64 -mattr=+m -riscv-enable-append-w-suffix -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=PREFER-W-INST %s
+
+define i32 @addiw(i32 %a) {
+; NO-PREFER-W-INST-LABEL: addiw:
+; NO-PREFER-W-INST: # %bb.0:
+; NO-PREFER-W-INST-NEXT: lui a1, 1
+; NO-PREFER-W-INST-NEXT: addi a1, a1, -1
+; NO-PREFER-W-INST-NEXT: addw a0, a0, a1
+; NO-PREFER-W-INST-NEXT: ret
+;
+; NO-STRIP-LABEL: addiw:
+; NO-STRIP: # %bb.0:
+; NO-STRIP-NEXT: lui a1, 1
+; NO-STRIP-NEXT: addiw a1, a1, -1
+; NO-STRIP-NEXT: addw a0, a0, a1
+; NO-STRIP-NEXT: ret
+;
+; PREFER-W-INST-LABEL: addiw:
+; PREFER-W-INST: # %bb.0:
+; PREFER-W-INST-NEXT: lui a1, 1
+; PREFER-W-INST-NEXT: addiw a1, a1, -1
+; PREFER-W-INST-NEXT: addw a0, a0, a1
+; PREFER-W-INST-NEXT: ret
+ %ret = add i32 %a, 4095
+ ret i32 %ret
+}
+
+define i32 @addw(i32 %a, i32 %b) {
+; NO-PREFER-W-INST-LABEL: addw:
+; NO-PREFER-W-INST: # %bb.0:
+; NO-PREFER-W-INST-NEXT: add a0, a0, a1
+; NO-PREFER-W-INST-NEXT: addiw a0, a0, 1024
+; NO-PREFER-W-INST-NEXT: ret
+;
+; NO-STRIP-LABEL: addw:
+; NO-STRIP: # %bb.0:
+; NO-STRIP-NEXT: addw a0, a0, a1
+; NO-STRIP-NEXT: addiw a0, a0, 1024
+; NO-STRIP-NEXT: ret
+;
+; PREFER-W-INST-LABEL: addw:
+; PREFER-W-INST: # %bb.0:
+; PREFER-W-INST-NEXT: addw a0, a0, a1
+; PREFER-W-INST-NEXT: addiw a0, a0, 1024
+; PREFER-W-INST-NEXT: ret
+ %add = add i32 %a, %b
+ %ret = add i32 %add, 1024
+ ret i32 %ret
+}
+
+define i32 @mulw(i32 %a, i32 %b) {
+; NO-PREFER-W-INST-LABEL: mulw:
+; NO-PREFER-W-INST: # %bb.0:
+; NO-PREFER-W-INST-NEXT: mul a1, a0, a1
+; NO-PREFER-W-INST-NEXT: mul a0, a0, a1
+; NO-PREFER-W-INST-NEXT: addiw a0, a0, 1024
+; NO-PREFER-W-INST-NEXT: ret
+;
+; NO-STRIP-LABEL: mulw:
+; NO-STRIP: # %bb.0:
+; NO-STRIP-NEXT: mulw a1, a0, a1
+; NO-STRIP-NEXT: mulw a0, a0, a1
+; NO-STRIP-NEXT: addiw a0, a0, 1024
+; NO-STRIP-NEXT: ret
+;
+; PREFER-W-INST-LABEL: mulw:
+; PREFER-W-INST: # %bb.0:
+; PREFER-W-INST-NEXT: mulw a1, a0, a1
+; PREFER-W-INST-NEXT: mulw a0, a0, a1
+; PREFER-W-INST-NEXT: addiw a0, a0, 1024
+; PREFER-W-INST-NEXT: ret
+ %mul1 = mul i32 %a, %b
+ %mul = mul i32 %a, %mul1
+ %ret = add i32 %mul, 1024
+ ret i32 %ret
+}
+
+define i32 @slliw(i32 %a) {
+; NO-PREFER-W-INST-LABEL: slliw:
+; NO-PREFER-W-INST: # %bb.0:
+; NO-PREFER-W-INST-NEXT: slli a0, a0, 1
+; NO-PREFER-W-INST-NEXT: addiw a0, a0, 1024
+; NO-PREFER-W-INST-NEXT: ret
+;
+; NO-STRIP-LABEL: slliw:
+; NO-STRIP: # %bb.0:
+; NO-STRIP-NEXT: slliw a0, a0, 1
+; NO-STRIP-NEXT: addiw a0, a0, 1024
+; NO-STRIP-NEXT: ret
+;
+; PREFER-W-INST-LABEL: slliw:
+; PREFER-W-INST: # %bb.0:
+; PREFER-W-INST-NEXT: slliw a0, a0, 1
+; PREFER-W-INST-NEXT: addiw a0, a0, 1024
+; PREFER-W-INST-NEXT: ret
+ %shl = shl i32 %a, 1
+ %ret = add i32 %shl, 1024
+ ret i32 %ret
+}
diff --git a/llvm/test/CodeGen/RISCV/prefer-w-inst.mir b/llvm/test/CodeGen/RISCV/prefer-w-inst.mir
new file mode 100644
index 00000000000000..2b60a3f74688eb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/prefer-w-inst.mir
@@ -0,0 +1,136 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-opt-w-instrs \
+# RUN: -mattr=+m -o - | FileCheck %s -check-prefixes=NO-PREFER-W-INST
+# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-opt-w-instrs \
+# RUN: -mattr=+m,+prefer-w-inst -o - | FileCheck %s -check-prefixes=PREFER-W-INST
+# RUN: llc %s -mtriple=riscv64 -run-pass=riscv-opt-w-instrs \
+# RUN: -mattr=+m -riscv-enable-append-w-suffix -o - | FileCheck %s -check-prefixes=PREFER-W-INST
+
+---
+name: addiw
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; NO-PREFER-W-INST-LABEL: name: addiw
+ ; NO-PREFER-W-INST: liveins: $x10, $x11
+ ; NO-PREFER-W-INST-NEXT: {{ $}}
+ ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; NO-PREFER-W-INST-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1
+ ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[ADDI]], 1
+ ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]]
+ ; NO-PREFER-W-INST-NEXT: PseudoRET
+ ;
+ ; PREFER-W-INST-LABEL: name: addiw
+ ; PREFER-W-INST: liveins: $x10, $x11
+ ; PREFER-W-INST-NEXT: {{ $}}
+ ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 1
+ ; PREFER-W-INST-NEXT: [[ADDIW1:%[0-9]+]]:gpr = ADDIW [[ADDIW]], 1
+ ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW1]]
+ ; PREFER-W-INST-NEXT: PseudoRET
+ %1:gpr = COPY $x10
+ %2:gpr = COPY $x11
+ %3:gpr = ADDI %1, 1
+ %4:gpr = ADDIW %3, 1
+ $x10 = COPY %4
+ PseudoRET
+...
+
+---
+name: addw
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; NO-PREFER-W-INST-LABEL: name: addw
+ ; NO-PREFER-W-INST: liveins: $x10, $x11
+ ; NO-PREFER-W-INST-NEXT: {{ $}}
+ ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; NO-PREFER-W-INST-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
+ ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[ADD]], 1
+ ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]]
+ ; NO-PREFER-W-INST-NEXT: PseudoRET
+ ;
+ ; PREFER-W-INST-LABEL: name: addw
+ ; PREFER-W-INST: liveins: $x10, $x11
+ ; PREFER-W-INST-NEXT: {{ $}}
+ ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; PREFER-W-INST-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
+ ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[ADDW]], 1
+ ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]]
+ ; PREFER-W-INST-NEXT: PseudoRET
+ %1:gpr = COPY $x10
+ %2:gpr = COPY $x11
+ %3:gpr = ADD %1, %2
+ %4:gpr = ADDIW %3, 1
+ $x10 = COPY %4
+ PseudoRET
+...
+
+---
+name: mulw
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; NO-PREFER-W-INST-LABEL: name: mulw
+ ; NO-PREFER-W-INST: liveins: $x10, $x11
+ ; NO-PREFER-W-INST-NEXT: {{ $}}
+ ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; NO-PREFER-W-INST-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]]
+ ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[MUL]], 1
+ ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]]
+ ; NO-PREFER-W-INST-NEXT: PseudoRET
+ ;
+ ; PREFER-W-INST-LABEL: name: mulw
+ ; PREFER-W-INST: liveins: $x10, $x11
+ ; PREFER-W-INST-NEXT: {{ $}}
+ ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; PREFER-W-INST-NEXT: [[MULW:%[0-9]+]]:gpr = MULW [[COPY]], [[COPY1]]
+ ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[MULW]], 1
+ ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]]
+ ; PREFER-W-INST-NEXT: PseudoRET
+ %1:gpr = COPY $x10
+ %2:gpr = COPY $x11
+ %3:gpr = MUL %1, %2
+ %4:gpr = ADDIW %3, 1
+ $x10 = COPY %4
+ PseudoRET
+...
+
+
+---
+name: slli
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; NO-PREFER-W-INST-LABEL: name: slli
+ ; NO-PREFER-W-INST: liveins: $x10, $x11
+ ; NO-PREFER-W-INST-NEXT: {{ $}}
+ ; NO-PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; NO-PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; NO-PREFER-W-INST-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], [[COPY1]]
+ ; NO-PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[SLLI]], 1
+ ; NO-PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]]
+ ; NO-PREFER-W-INST-NEXT: PseudoRET
+ ;
+ ; PREFER-W-INST-LABEL: name: slli
+ ; PREFER-W-INST: liveins: $x10, $x11
+ ; PREFER-W-INST-NEXT: {{ $}}
+ ; PREFER-W-INST-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+ ; PREFER-W-INST-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
+ ; PREFER-W-INST-NEXT: [[SLLIW:%[0-9]+]]:gpr = SLLIW [[COPY]], [[COPY1]]
+ ; PREFER-W-INST-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[SLLIW]], 1
+ ; PREFER-W-INST-NEXT: $x10 = COPY [[ADDIW]]
+ ; PREFER-W-INST-NEXT: PseudoRET
+ %1:gpr = COPY $x10
+ %2:gpr = COPY $x11
+ %3:gpr = SLLI %1, %2
+ %4:gpr = ADDIW %3, 1
+ $x10 = COPY %4
+ PseudoRET
+...
diff --git a/llvm/test/CodeGen/RISCV/strip-w-suffix.ll b/llvm/test/CodeGen/RISCV/strip-w-suffix.ll
deleted file mode 100644
index 4124b3d0d360d2..00000000000000
--- a/llvm/test/CodeGen/RISCV/strip-w-suffix.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=STRIP %s
-; RUN: llc -mtriple=riscv64 -mattr=+m,+no-strip-w-suffix -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefixes=NO-STRIP %s
-
-define i32 @addiw(i32 %a) {
-; STRIP-LABEL: addiw:
-; STRIP: # %bb.0:
-; STRIP-NEXT: lui a1, 1
-; STRIP-NEXT: addi a1, a1, -1
-; STRIP-NEXT: addw a0, a0, a1
-; STRIP-NEXT: ret
-;
-; NO-STRIP-LABEL: addiw:
-; NO-STRIP: # %bb.0:
-; NO-STRIP-NEXT: lui a1, 1
-; NO-STRIP-NEXT: addiw a1, a1, -1
-; NO-STRIP-NEXT: addw a0, a0, a1
-; NO-STRIP-NEXT: ret
- %ret = add i32 %a, 4095
- ret i32 %ret
-}
-
-define i32 @addw(i32 %a, i32 %b) {
-; STRIP-LABEL: addw:
-; STRIP: # %bb.0:
-; STRIP-NEXT: add a0, a0, a1
-; STRIP-NEXT: addiw a0, a0, 1024
-; STRIP-NEXT: ret
-;
-; NO-STRIP-LABEL: addw:
-; NO-STRIP: # %bb.0:
-; NO-STRIP-NEXT: addw a0, a0, a1
-; NO-STRIP-NEXT: addiw a0, a0, 1024
-; NO-STRIP-NEXT: ret
- %add = add i32 %a, %b
- %ret = add i32 %add, 1024
- ret i32 %ret
-}
-
-define i32 @mulw(i32 %a, i32 %b) {
-; STRIP-LABEL: mulw:
-; STRIP: # %bb.0:
-; STRIP-NEXT: mul a0, a0, a1
-; STRIP-NEXT: addiw a0, a0, 1024
-; STRIP-NEXT: ret
-;
-; NO-STRIP-LABEL: mulw:
-; NO-STRIP: # %bb.0:
-; NO-STRIP-NEXT: mulw a0, a0, a1
-; NO-STRIP-NEXT: addiw a0, a0, 1024
-; NO-STRIP-NEXT: ret
- %mul = mul i32 %a, %b
- %ret = add i32 %mul, 1024
- ret i32 %ret
-}
-
-define i32 @slliw(i32 %a) {
-; STRIP-LABEL: slliw:
-; STRIP: # %bb.0:
-; STRIP-NEXT: slli a0, a0, 1
-; STRIP-NEXT: addiw a0, a0, 1024
-; STRIP-NEXT: ret
-;
-; NO-STRIP-LABEL: slliw:
-; NO-STRIP: # %bb.0:
-; NO-STRIP-NEXT: slliw a0, a0, 1
-; NO-STRIP-NEXT: addiw a0, a0, 1024
-; NO-STRIP-NEXT: ret
- %shl = shl i32 %a, 1
- %ret = add i32 %shl, 1024
- ret i32 %ret
-}
|
wangpc-pp
requested review from
asb,
preames,
dtcxzyw,
topperc,
lukel97 and
michaelmaitland
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
Created using spr 1.3.6-beta.1
dtcxzyw
reviewed
Apr 1, 2024
Created using spr 1.3.6-beta.1
Created using spr 1.3.6-beta.1
dtcxzyw
reviewed
Apr 3, 2024
| MI.setDesc(TII.get(WOpc)); | ||
| MI.clearFlag(MachineInstr::MIFlag::NoSWrap); | ||
| MI.clearFlag(MachineInstr::MIFlag::NoUWrap); | ||
| MI.clearFlag(MachineInstr::MIFlag::IsExact); |
There was a problem hiding this comment.
Can you add some tests for flags dropping?
There was a problem hiding this comment.
It's the same as RISCVOptWInstrs::removeSExtWInstrs:
llvm-project/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
Lines 648 to 657 in a8c5975
I don't know how to test it actually.
topperc
reviewed
Apr 3, 2024
Created using spr 1.3.6-beta.1
|
Ping. |
wangpc-pp
deleted the
users/wangpc-pp/spr/riscv-generate-more-w-instructons
branch
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We rename
TuneNoStripWSuffixtoTunePreferWInst.If all the users of an instruction just use the low 32 bits, we can
convert it to its W variant.
A quick test on Coremark (
-O3 -march=rv64gc):