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[RISCV] Lower (vector_interleave X, undef) to (vzext_vl X). #87283

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[RISCV] Lower (vector_interleave X, undef) to (vzext_vl X). #87283

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982160f
[RISCV] Add test for miscompile of vector.interleave when odd vector …
topperc Apr 1, 2024
97bf6a0
[RISCV] Lower (vector_interleave X, undef) to (vzext_vl X).
topperc Apr 1, 2024
68b6802
fixup! clang-format and remove FIXME from test.
topperc Apr 1, 2024
0557582
Merge remote-tracking branch 'origin/main' into pr/interleave-poison
topperc Apr 2, 2024
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11 changes: 10 additions & 1 deletion llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4624,7 +4624,13 @@ static SDValue getWideningInterleave(SDValue EvenV, SDValue OddV,
SDValue Passthru = DAG.getUNDEF(WideContainerVT);

SDValue Interleaved;
if (Subtarget.hasStdExtZvbb()) {
if (OddV.isUndef()) {
// If OddV is undef, this is a zero extend.
// FIXME: Not only does this optimize the code, it fixes some correctness
// issues because MIR does not have freeze.
Interleaved =
DAG.getNode(RISCVISD::VZEXT_VL, DL, WideContainerVT, EvenV, Mask, VL);
} else if (Subtarget.hasStdExtZvbb()) {
// Interleaved = (OddV << VecVT.getScalarSizeInBits()) + EvenV.
SDValue OffsetVec =
DAG.getSplatVector(VecContainerVT, DL,
Expand All @@ -4635,6 +4641,9 @@ static SDValue getWideningInterleave(SDValue EvenV, SDValue OddV,
Interleaved = DAG.getNode(RISCVISD::VWADDU_W_VL, DL, WideContainerVT,
Interleaved, EvenV, Passthru, Mask, VL);
} else {
// FIXME: We should freeze the odd vector here. We already handled the case
// of provably undef/poison above.

// Widen EvenV and OddV with 0s and add one copy of OddV to EvenV with
// vwaddu.vv
Interleaved = DAG.getNode(RISCVISD::VWADDU_VL, DL, WideContainerVT, EvenV,
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18 changes: 18 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll
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Expand Up @@ -656,6 +656,24 @@ define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv8f64(<vscale x 8 x
ret <vscale x 16 x double> %res
}

define <vscale x 8 x i32> @vector_interleave_nxv8i32_nxv4i32_poison(<vscale x 4 x i32> %a) {
; CHECK-LABEL: vector_interleave_nxv8i32_nxv4i32_poison:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave_nxv8i32_nxv4i32_poison:
; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; ZVBB-NEXT: vzext.vf2 v12, v8
; ZVBB-NEXT: vmv.v.v v8, v12
; ZVBB-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.experimental.vector.interleave2.nxv8i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> poison)
ret <vscale x 8 x i32> %res
}

declare <vscale x 64 x half> @llvm.experimental.vector.interleave2.nxv64f16(<vscale x 32 x half>, <vscale x 32 x half>)
declare <vscale x 32 x float> @llvm.experimental.vector.interleave2.nxv32f32(<vscale x 16 x float>, <vscale x 16 x float>)
declare <vscale x 16 x double> @llvm.experimental.vector.interleave2.nxv16f64(<vscale x 8 x double>, <vscale x 8 x double>)