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[GlobalISel] Fix the infinite loop issue in commute_int_constant_to_rhs #87426

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17 changes: 9 additions & 8 deletions llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -6276,14 +6276,15 @@ bool CombinerHelper::matchShiftsTooBig(MachineInstr &MI) {
bool CombinerHelper::matchCommuteConstantToRHS(MachineInstr &MI) {
Register LHS = MI.getOperand(1).getReg();
Register RHS = MI.getOperand(2).getReg();
auto *LHSDef = MRI.getVRegDef(LHS);
if (getIConstantVRegVal(LHS, MRI).has_value())
return true;

// LHS may be a G_CONSTANT_FOLD_BARRIER. If so we commute
// as long as we don't already have a constant on the RHS.
if (LHSDef->getOpcode() != TargetOpcode::G_CONSTANT_FOLD_BARRIER)
return false;
if (!getIConstantVRegVal(LHS, MRI)) {
// Skip commuting if LHS is not a constant. But, LHS may be a
// G_CONSTANT_FOLD_BARRIER. If so we commute as long as we don't already
// have a constant on the RHS.
if (MRI.getVRegDef(LHS)->getOpcode() !=
TargetOpcode::G_CONSTANT_FOLD_BARRIER)
return false;
}
// Commute as long as RHS is not a constant or G_CONSTANT_FOLD_BARRIER.
return MRI.getVRegDef(RHS)->getOpcode() !=
TargetOpcode::G_CONSTANT_FOLD_BARRIER &&
!getIConstantVRegVal(RHS, MRI);
Expand Down
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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Can you merge this test with test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir

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Can you merge this test with test/CodeGen/AArch64/GlobalISel/combine-const-fold-barrier-rhs.mir

This test needs --aarch64prelegalizercombiner-disable-rule=constant_fold_binop to trigger issue. That makes the merge complicated. Shall we leave as it is.

# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner %s -o - \
# RUN: --aarch64prelegalizercombiner-disable-rule=constant_fold_binop | FileCheck %s

# `constant_fold_binop` is disabled to trigger the infinite loop in `commute_int_constant_to_rhs`.

---
name: add
tracksRegLiveness: true
body: |
bb.0:
liveins: $s0

; CHECK-LABEL: name: add
; CHECK: liveins: $s0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %c0:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: %c1:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: %add:_(s32) = G_ADD %c0, %c1
; CHECK-NEXT: $s0 = COPY %add(s32)
; CHECK-NEXT: RET_ReallyLR
%c0:_(s32) = G_CONSTANT i32 1
%c1:_(s32) = G_CONSTANT i32 2
%add:_(s32) = G_ADD %c0, %c1
$s0 = COPY %add
RET_ReallyLR

...
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Maybe add a vector version?