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AMDGPU: Undo atomicrmw add/sub/xor 0 -> atomicrmw or canonicalization #87533

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merged 2 commits into from
Apr 12, 2024
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AMDGPU: Undo atomicrmw add/sub/xor 0 -> atomicrmw or canonicalization #87533

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AMDGPU: Undo atomicrmw add/sub/xor 0 -> atomicrmw or canonicalization
arsenm Apr 3, 2024
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arsenm Apr 12, 2024
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27 changes: 25 additions & 2 deletions llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16027,6 +16027,19 @@ SITargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
SSID == RMW->getContext().getOrInsertSyncScopeID("one-as");

switch (RMW->getOperation()) {
case AtomicRMWInst::Sub:
case AtomicRMWInst::Or:
case AtomicRMWInst::Xor: {
// Atomic sub/or/xor do not work over PCI express, but atomic add
// does. InstCombine transforms these with 0 to or, so undo that.
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How does this Lowering hook work? Does it prevent IC from doing the or canonicalization?
If so then it's not really undoing it, just preventing it from happening, right?

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No, this is a codegen hook for the AtomicExpand pass. InstCombine does this transform and then we run the expand in codegen to undo it. Someone could also have written the code this way in the first place

if (HasSystemScope && AMDGPU::isFlatGlobalAddrSpace(AS)) {
if (Constant *ConstVal = dyn_cast<Constant>(RMW->getValOperand());
ConstVal && ConstVal->isNullValue())
return AtomicExpansionKind::Expand;
}

break;
}
case AtomicRMWInst::FAdd: {
Type *Ty = RMW->getType();

Expand Down Expand Up @@ -16312,14 +16325,24 @@ bool SITargetLowering::checkForPhysRegDependency(
}

void SITargetLowering::emitExpandAtomicRMW(AtomicRMWInst *AI) const {
AtomicRMWInst::BinOp Op = AI->getOperation();

if (Op == AtomicRMWInst::Sub || Op == AtomicRMWInst::Or ||
Op == AtomicRMWInst::Xor) {
// atomicrmw or %ptr, 0 -> atomicrmw add %ptr, 0
assert(cast<Constant>(AI->getValOperand())->isNullValue() &&
"this cannot be replaced with add");
AI->setOperation(AtomicRMWInst::Add);
return;
}

assert(Subtarget->hasAtomicFaddInsts() &&
"target should have atomic fadd instructions");
assert(AI->getType()->isFloatTy() &&
AI->getPointerAddressSpace() == AMDGPUAS::FLAT_ADDRESS &&
"generic atomicrmw expansion only supports FP32 operand in flat "
"address space");
assert(AI->getOperation() == AtomicRMWInst::FAdd &&
"only fadd is supported for now");
assert(Op == AtomicRMWInst::FAdd && "only fadd is supported for now");

// Given: atomicrmw fadd ptr %addr, float %val ordering
//
Expand Down
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