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[RISCV][GISel] Make register bank selection for unary and binary arithmetic ops more generic. #87593

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Merged
merged 1 commit into from
Apr 4, 2024
Merged

[RISCV][GISel] Make register bank selection for unary and binary arithmetic ops more generic. #87593

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45 changes: 28 additions & 17 deletions llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -290,16 +290,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {

switch (Opc) {
case TargetOpcode::G_ADD:
case TargetOpcode::G_SUB: {
if (MRI.getType(MI.getOperand(0).getReg()).isVector()) {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
return getInstructionMapping(
DefaultMappingID, /*Cost=*/1,
getVRBValueMapping(Ty.getSizeInBits().getKnownMinValue()),
NumOperands);
}
}
LLVM_FALLTHROUGH;
case TargetOpcode::G_SUB:
case TargetOpcode::G_SHL:
case TargetOpcode::G_ASHR:
case TargetOpcode::G_LSHR:
Expand All @@ -320,10 +311,6 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_PTR_ADD:
case TargetOpcode::G_PTRTOINT:
case TargetOpcode::G_INTTOPTR:
case TargetOpcode::G_SEXTLOAD:
case TargetOpcode::G_ZEXTLOAD:
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, GPRValueMapping,
NumOperands);
case TargetOpcode::G_FADD:
case TargetOpcode::G_FSUB:
case TargetOpcode::G_FMUL:
Expand All @@ -334,10 +321,34 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_FMAXNUM:
case TargetOpcode::G_FMINNUM: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
return getInstructionMapping(DefaultMappingID, /*Cost=*/1,
getFPValueMapping(Ty.getSizeInBits()),
NumOperands);
TypeSize Size = Ty.getSizeInBits();

const ValueMapping *Mapping;
if (Ty.isVector())
Mapping = getVRBValueMapping(Size.getKnownMinValue());
else if (isPreISelGenericFloatingPointOpcode(Opc))
Mapping = getFPValueMapping(Size.getFixedValue());
else
Mapping = GPRValueMapping;

#ifndef NDEBUG
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Why the #ifndef NDEBUG?

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As we discussed offline, the loop only exists because of the assert in it. If those asserts will be compiled to nothing, there is no need for the loop or any variables in int. AArch64 does something similar.

// Make sure all the operands are using similar size and type.
for (unsigned Idx = 1; Idx != NumOperands; ++Idx) {
LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());
assert(Ty.isVector() == OpTy.isVector() &&
"Operand has incompatible type");
// Don't check size for GPR.
if (OpTy.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
assert(Size == OpTy.getSizeInBits() && "Operand has incompatible size");
}
#endif // End NDEBUG

return getInstructionMapping(DefaultMappingID, 1, Mapping, NumOperands);
}
case TargetOpcode::G_SEXTLOAD:
case TargetOpcode::G_ZEXTLOAD:
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, GPRValueMapping,
NumOperands);
case TargetOpcode::G_IMPLICIT_DEF: {
Register Dst = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(Dst);
Expand Down