[AArch64] Fix to Neoverse V2 scheduling model

[mgabka]

The size of ROB was incorrecty copied from the Neoverse N2, while it has actually higher value as descibed in
https://community.arm.com/arm-community-blogs/b/infrastructure-solutions-blog/posts/arm-neoverse-v2-platform-best-in-class-cloud-and-ai-ml-performance

[llvmbot]

@llvm/pr-subscribers-backend-aarch64

Author: Maciej Gabka (mgabka)

Changes

The size of ROB was incorrecty copied from the Neoverse N2, while it has actually higher value as descibed in
https://community.arm.com/arm-community-blogs/b/infrastructure-solutions-blog/posts/arm-neoverse-v2-platform-best-in-class-cloud-and-ai-ml-performance

---

Full diff: https://github.com/llvm/llvm-project/pull/88130.diff

1 Files Affected:

• (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td (+1-1)

diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 4d7f44e7b9b9ab..7fed8fed900171 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -15,7 +15,7 @@
 
 def NeoverseV2Model : SchedMachineModel {
   let IssueWidth            =  16; // Micro-ops dispatched at a time.
-  let MicroOpBufferSize     = 160; // Entries in micro-op re-order buffer. NOTE: Copied from N2.
+  let MicroOpBufferSize     = 320; // Entries in micro-op re-order buffer.
   let LoadLatency           =   4; // Optimistic load latency.
   let MispredictPenalty     =  10; // Extra cycles for mispredicted branch.  NOTE: Copied from N2.
   let LoopMicroOpBufferSize =  16; // NOTE: Copied from Cortex-A57.

[davemgreen]

Is adding a test for this is difficult, as it doesn't modify much in practice? The change sounds sensible.

[mgabka]

Is adding a test for this is difficult, as it doesn't modify much in practice? The change sounds sensible.

Yeah, to me looks like this value does not impact much, in most cases it is just checked if it is !=0 or ==1, the only one place I found where the actual value matters is here

llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp

Line 3360 in 4e85e1f

Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;

,

that code seems to be added by c01b004 and the EnableCyclicPath is now by defult true, but setting it to false does not break any tests for me.

[davemgreen]

The change looks good. Thanks