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Update LowerContractionToSMMLAPattern to ingnore matvec #88288

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Merged
merged 1 commit into from
Apr 10, 2024
Merged

Update LowerContractionToSMMLAPattern to ingnore matvec #88288

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3 changes: 3 additions & 0 deletions mlir/lib/Dialect/ArmNeon/Transforms/LowerContractionToSMMLAPattern.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,9 @@ class LowerContractionToSMMLAPattern
// Note: RHS is not transposed.
mlir::VectorType lhsType = op.getLhsType();
mlir::VectorType rhsType = op.getRhsType();
// Avoid 0-D vectors and 1-D rhs:
if (!lhsType.hasRank() || !rhsType.hasRank() || rhsType.getRank() < 2)
return failure();
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Since 0-D vectors can also reach this point, could you add another check making sure that if any of the operands doesn't have a rank, we also bail out (+ test for that)?

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I don't think vector.contract supports 0-D vectors. I couldn't create one without hitting errors:
error: unexpected error: 'vector.contract' op operand #0 must be vector of any type values, but got 'vector<i32>'

I did add "hasRank" check just in case.

auto dimM = lhsType.getRank() == 1 ? 1 : lhsType.getDimSize(0);
auto dimN = rhsType.getDimSize(0);
auto dimK = rhsType.getDimSize(1);
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11 changes: 11 additions & 0 deletions mlir/test/Dialect/ArmNeon/lower-to-arm-neon.mlir
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Expand Up @@ -258,3 +258,14 @@ func.func @test_lower_vector_arm_neon_vecmat_unroll_leading_dim(%lhs: vector<1x8
%res = vector.contract {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d2)>, affine_map<(d0, d1, d2) -> (d1, d2)>, affine_map<(d0, d1, d2) -> (d0, d1)>], iterator_types = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %lhs_extsi, %rhs_extsi, %acc : vector<1x8xi32>, vector<8x8xi32> into vector<1x8xi32>
return %res : vector<1x8xi32>
}

// -----

// CHECK-LABEL: func.func @test_lower_vector_arm_neon_matvec
// CHECK-NOT: arm_neon.intr.smmla
func.func @test_lower_vector_arm_neon_matvec(%lhs: vector<8x8xi8>, %rhs: vector<8xi8>, %acc : vector<8xi32>) -> vector<8xi32> {
%rhs_extsi= arith.extsi %rhs : vector<8xi8> to vector<8xi32>
%lhs_extsi = arith.extsi %lhs : vector<8x8xi8> to vector<8x8xi32>
%res = vector.contract {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,affine_map<(d0, d1) -> (d1)>, affine_map<(d0, d1) -> (d0)>], iterator_types = ["parallel", "reduction"], kind = #vector.kind<add>} %lhs_extsi, %rhs_extsi, %acc : vector<8x8xi32>, vector<8xi32> into vector<8xi32>
return %res : vector<8xi32>
}