Skip to content

[LLVM][CodeGen][SVE] rev(whilelo(a,b)) -> whilehi(b,a). #88294

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Apr 23, 2024
Merged

[LLVM][CodeGen][SVE] rev(whilelo(a,b)) -> whilehi(b,a). #88294

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
ff5a750
Add tests for rev(while##(a,b).
paulwalker-arm Apr 10, 2024
4090b5b
[LLVM][CodeGen][SVE] rev(whilelo(a,b)) -> whilehi(b,a).
paulwalker-arm Apr 10, 2024
8af2994
Prevent unsafe transformation for the equality variants.
paulwalker-arm Apr 17, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
34 changes: 17 additions & 17 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2037,15 +2037,15 @@ let Predicates = [HasSVEorSME] in {
defm FCMEQ_PPzZ0 : sve_fp_2op_p_pd<0b100, "fcmeq", SETOEQ, SETEQ, SETOEQ, SETEQ>;
defm FCMNE_PPzZ0 : sve_fp_2op_p_pd<0b110, "fcmne", SETUNE, SETNE, SETUNE, SETNE>;

defm WHILELT_PWW : sve_int_while4_rr<0b010, "whilelt", int_aarch64_sve_whilelt>;
defm WHILELE_PWW : sve_int_while4_rr<0b011, "whilele", int_aarch64_sve_whilele>;
defm WHILELO_PWW : sve_int_while4_rr<0b110, "whilelo", int_aarch64_sve_whilelo>;
defm WHILELS_PWW : sve_int_while4_rr<0b111, "whilels", int_aarch64_sve_whilels>;
defm WHILELT_PWW : sve_int_while4_rr<0b010, "whilelt", int_aarch64_sve_whilelt, int_aarch64_sve_whilegt>;
defm WHILELE_PWW : sve_int_while4_rr<0b011, "whilele", int_aarch64_sve_whilele, null_frag>;
defm WHILELO_PWW : sve_int_while4_rr<0b110, "whilelo", int_aarch64_sve_whilelo, int_aarch64_sve_whilehi>;
defm WHILELS_PWW : sve_int_while4_rr<0b111, "whilels", int_aarch64_sve_whilels, null_frag>;

defm WHILELT_PXX : sve_int_while8_rr<0b010, "whilelt", int_aarch64_sve_whilelt>;
defm WHILELE_PXX : sve_int_while8_rr<0b011, "whilele", int_aarch64_sve_whilele>;
defm WHILELO_PXX : sve_int_while8_rr<0b110, "whilelo", int_aarch64_sve_whilelo>;
defm WHILELS_PXX : sve_int_while8_rr<0b111, "whilels", int_aarch64_sve_whilels>;
defm WHILELT_PXX : sve_int_while8_rr<0b010, "whilelt", int_aarch64_sve_whilelt, int_aarch64_sve_whilegt>;
defm WHILELE_PXX : sve_int_while8_rr<0b011, "whilele", int_aarch64_sve_whilele, null_frag>;
defm WHILELO_PXX : sve_int_while8_rr<0b110, "whilelo", int_aarch64_sve_whilelo, int_aarch64_sve_whilehi>;
defm WHILELS_PXX : sve_int_while8_rr<0b111, "whilels", int_aarch64_sve_whilels, null_frag>;

def CTERMEQ_WW : sve_int_cterm<0b0, 0b0, "ctermeq", GPR32>;
def CTERMNE_WW : sve_int_cterm<0b0, 0b1, "ctermne", GPR32>;
Expand Down Expand Up @@ -3792,15 +3792,15 @@ let Predicates = [HasSVE2orSME] in {
defm TBX_ZZZ : sve2_int_perm_tbx<"tbx", 0b01, int_aarch64_sve_tbx>;

// SVE2 integer compare scalar count and limit
defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege", int_aarch64_sve_whilege>;
defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt", int_aarch64_sve_whilegt>;
defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs", int_aarch64_sve_whilehs>;
defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi", int_aarch64_sve_whilehi>;

defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege", int_aarch64_sve_whilege>;
defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt", int_aarch64_sve_whilegt>;
defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs", int_aarch64_sve_whilehs>;
defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi", int_aarch64_sve_whilehi>;
defm WHILEGE_PWW : sve_int_while4_rr<0b000, "whilege", int_aarch64_sve_whilege, null_frag>;
defm WHILEGT_PWW : sve_int_while4_rr<0b001, "whilegt", int_aarch64_sve_whilegt, int_aarch64_sve_whilelt>;
defm WHILEHS_PWW : sve_int_while4_rr<0b100, "whilehs", int_aarch64_sve_whilehs, null_frag>;
defm WHILEHI_PWW : sve_int_while4_rr<0b101, "whilehi", int_aarch64_sve_whilehi, int_aarch64_sve_whilelo>;

defm WHILEGE_PXX : sve_int_while8_rr<0b000, "whilege", int_aarch64_sve_whilege, null_frag>;
defm WHILEGT_PXX : sve_int_while8_rr<0b001, "whilegt", int_aarch64_sve_whilegt, int_aarch64_sve_whilelt>;
defm WHILEHS_PXX : sve_int_while8_rr<0b100, "whilehs", int_aarch64_sve_whilehs, null_frag>;
defm WHILEHI_PXX : sve_int_while8_rr<0b101, "whilehi", int_aarch64_sve_whilehi, int_aarch64_sve_whilelo>;

// SVE2 pointer conflict compare
defm WHILEWR_PXX : sve2_int_while_rr<0b0, "whilewr", "int_aarch64_sve_whilewr">;
Expand Down
24 changes: 22 additions & 2 deletions llvm/lib/Target/AArch64/SVEInstrFormats.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5359,7 +5359,8 @@ class sve_int_while_rr<bits<2> sz8_64, bits<4> opc, string asm,
let isWhile = 1;
}

multiclass sve_int_while4_rr<bits<3> opc, string asm, SDPatternOperator op> {
multiclass sve_int_while4_rr<bits<3> opc, string asm, SDPatternOperator op,
SDPatternOperator rev_op> {
def _B : sve_int_while_rr<0b00, { 0, opc }, asm, GPR32, PPR8>;
def _H : sve_int_while_rr<0b01, { 0, opc }, asm, GPR32, PPR16>;
def _S : sve_int_while_rr<0b10, { 0, opc }, asm, GPR32, PPR32>;
Expand All @@ -5369,9 +5370,19 @@ multiclass sve_int_while4_rr<bits<3> opc, string asm, SDPatternOperator op> {
def : SVE_2_Op_Pat<nxv8i1, op, i32, i32, !cast<Instruction>(NAME # _H)>;
def : SVE_2_Op_Pat<nxv4i1, op, i32, i32, !cast<Instruction>(NAME # _S)>;
def : SVE_2_Op_Pat<nxv2i1, op, i32, i32, !cast<Instruction>(NAME # _D)>;

def : Pat<(nxv16i1 (vector_reverse (rev_op i32:$op2, i32:$op1))),
(!cast<Instruction>(NAME # "_B") $op1, $op2)>;
def : Pat<(nxv8i1 (vector_reverse (rev_op i32:$op2, i32:$op1))),
(!cast<Instruction>(NAME # "_H") $op1, $op2)>;
def : Pat<(nxv4i1 (vector_reverse (rev_op i32:$op2, i32:$op1))),
(!cast<Instruction>(NAME # "_S") $op1, $op2)>;
def : Pat<(nxv2i1 (vector_reverse (rev_op i32:$op2, i32:$op1))),
(!cast<Instruction>(NAME # "_D") $op1, $op2)>;
}

multiclass sve_int_while8_rr<bits<3> opc, string asm, SDPatternOperator op> {
multiclass sve_int_while8_rr<bits<3> opc, string asm, SDPatternOperator op,
SDPatternOperator rev_op> {
def _B : sve_int_while_rr<0b00, { 1, opc }, asm, GPR64, PPR8>;
def _H : sve_int_while_rr<0b01, { 1, opc }, asm, GPR64, PPR16>;
def _S : sve_int_while_rr<0b10, { 1, opc }, asm, GPR64, PPR32>;
Expand All @@ -5381,6 +5392,15 @@ multiclass sve_int_while8_rr<bits<3> opc, string asm, SDPatternOperator op> {
def : SVE_2_Op_Pat<nxv8i1, op, i64, i64, !cast<Instruction>(NAME # _H)>;
def : SVE_2_Op_Pat<nxv4i1, op, i64, i64, !cast<Instruction>(NAME # _S)>;
def : SVE_2_Op_Pat<nxv2i1, op, i64, i64, !cast<Instruction>(NAME # _D)>;

def : Pat<(nxv16i1 (vector_reverse (rev_op i64:$op2, i64:$op1))),
(!cast<Instruction>(NAME # "_B") $op1, $op2)>;
def : Pat<(nxv8i1 (vector_reverse (rev_op i64:$op2, i64:$op1))),
(!cast<Instruction>(NAME # "_H") $op1, $op2)>;
def : Pat<(nxv4i1 (vector_reverse (rev_op i64:$op2, i64:$op1))),
(!cast<Instruction>(NAME # "_S") $op1, $op2)>;
def : Pat<(nxv2i1 (vector_reverse (rev_op i64:$op2, i64:$op1))),
(!cast<Instruction>(NAME # "_D") $op1, $op2)>;
}

class sve2_int_while_rr<bits<2> sz8_64, bits<1> rw, string asm,
Expand Down
Loading