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[RISCV] Support uimm32 immediates in RISCVInstrInfo::movImm for RV32. #88464

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Merged
merged 1 commit into from
Apr 12, 2024
Merged

[RISCV] Support uimm32 immediates in RISCVInstrInfo::movImm for RV32. #88464

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11 changes: 9 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -767,8 +767,15 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
bool DstIsDead) const {
Register SrcReg = RISCV::X0;

if (!STI.is64Bit() && !isInt<32>(Val))
report_fatal_error("Should only materialize 32-bit constants for RV32");
// For RV32, allow a sign or unsigned 32 bit value.
if (!STI.is64Bit() && !isInt<32>(Val)) {
// If have a uimm32 it will still fit in a register so we can allow it.
if (!isUInt<32>(Val))
report_fatal_error("Should only materialize 32-bit constants for RV32");

// Sign extend for generateInstSeq.
Val = SignExtend64<32>(Val);
}

RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, STI);
assert(!Seq.empty());
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26 changes: 26 additions & 0 deletions llvm/test/CodeGen/RISCV/pr88365.ll
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@@ -0,0 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=riscv32 | FileCheck %s

define void @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -2032
; CHECK-NEXT: .cfi_def_cfa_offset 2032
; CHECK-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -4
; CHECK-NEXT: li a0, -2048
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Is this right?

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I don’t think it is.

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It is correct. The stack offset needs to be 0xfffff800 as an unsigned number. Which is -2048.

; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_def_cfa_offset -16
; CHECK-NEXT: addi a0, sp, 4
; CHECK-NEXT: call use
; CHECK-NEXT: li a0, -2048
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 2032
; CHECK-NEXT: ret
%1 = alloca [1073741818 x i32], align 4
call void @use(ptr %1)
ret void
}

declare void @use(ptr)