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[RISCV] Remove mayLoad = 1 from store-conditional #88470

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Merged
merged 1 commit into from
Apr 12, 2024
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[RISCV] Remove mayLoad = 1 from store-conditional #88470

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17 changes: 15 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoA.td
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,19 @@ multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class SC_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
: RVInstRAtomic<0b00011, aq, rl, funct3, OPC_AMO,
(outs GPR:$rd), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
opcodestr, "$rd, $rs2, $rs1">;

multiclass SC_r_aq_rl<bits<3> funct3, string opcodestr> {
def "" : SC_r<0, 0, funct3, opcodestr>;
def _AQ : SC_r<1, 0, funct3, opcodestr # ".aq">;
def _RL : SC_r<0, 1, funct3, opcodestr # ".rl">;
def _AQ_RL : SC_r<1, 1, funct3, opcodestr # ".aqrl">;
}

let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
: RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
Expand All @@ -49,7 +62,7 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {

let Predicates = [HasStdExtAOrZalrsc], IsSignExtendingOpW = 1 in {
defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">,
defm SC_W : SC_r_aq_rl<0b010, "sc.w">,
Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
} // Predicates = [HasStdExtAOrZalrsc], IsSignExtendingOpW = 1

Expand All @@ -76,7 +89,7 @@ defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">,

let Predicates = [HasStdExtAOrZalrsc, IsRV64] in {
defm LR_D : LR_r_aq_rl<0b011, "lr.d">, Sched<[WriteAtomicLDD, ReadAtomicLDD]>;
defm SC_D : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">,
defm SC_D : SC_r_aq_rl<0b011, "sc.d">,
Sched<[WriteAtomicSTD, ReadAtomicSTD, ReadAtomicSTD]>;
} // Predicates = [HasStdExtAOrZalrsc, IsRV64]

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