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[llvm-exegesis] Add support for alder lake #88967

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Merged
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Apr 23, 2024
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[llvm-exegesis] Add support for alder lake #88967

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[llvm-exegesis] Add support for alder lake
boomanaiden154 Apr 16, 2024
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Address reviewer feedback
boomanaiden154 Apr 20, 2024
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boomanaiden154 Apr 20, 2024
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16 changes: 16 additions & 0 deletions llvm/lib/Target/X86/X86PfmCounters.td
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Original file line number Diff line number Diff line change
Expand Up @@ -204,6 +204,22 @@ def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>;
def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>;
def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>;

def AlderLakePfmCounters : ProcPfmCounters {
let CycleCounter = UnhaltedCoreCyclesPfmCounter;
let UopsCounter = UopsIssuedPfmCounter;
let IssueCounters = [
PfmIssueCounter<"ADLPPort00", "uops_dispatched_port:port_0">,
PfmIssueCounter<"ADLPPort01", "uops_dispatched_port:port_1">,
PfmIssueCounter<"ADLPPort02_03_10", "uops_dispatched_port:port_2_3_10">,
PfmIssueCounter<"ADLPPort04_09", "uops_dispatched_port:port_4_9">,
PfmIssueCounter<"ADLPPort05_11", "uops_dispatched_port:port_5_11">,
PfmIssueCounter<"ADLPPort06", "uops_dispatched_port:port_6">,
PfmIssueCounter<"ADLPPort07_08", "uops_dispatched_port:port_7_8">
];
let ValidationCounters = DefaultIntelPfmValidationCounters;
}
def : PfmCountersBinding<"alderlake", AlderLakePfmCounters>;

// AMD X86 Counters.
defvar DefaultAMDPfmValidationCounters = [
PfmValidationCounter<InstructionRetired, "RETIRED_INSTRUCTIONS">,
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6 changes: 6 additions & 0 deletions llvm/lib/Target/X86/X86SchedAlderlakeP.td
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Expand Up @@ -60,6 +60,8 @@ def ADLPPort01_05_10 : ProcResGroup<[ADLPPort01, ADLPPort05, ADLPPort10]>;
def ADLPPort02_03 : ProcResGroup<[ADLPPort02, ADLPPort03]>;
def ADLPPort02_03_07 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07]>;
def ADLPPort02_03_11 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort11]>;
def ADLPPort02_03_10 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort10]>;
def ADLPPort05_11 : ProcResGroup<[ADLPPort05, ADLPPort11]>;
def ADLPPort07_08 : ProcResGroup<[ADLPPort07, ADLPPort08]>;

// EU has 112 reservation stations.
Expand All @@ -79,6 +81,10 @@ def ADLPPort02_03_07_08_11 : ProcResGroup<[ADLPPort02, ADLPPort03, ADLPPort07,
let BufferSize = 72;
}

def ADLPPortAny : ProcResGroup<[ADLPPort00, ADLPPort01, ADLPPort02, ADLPPort03,
ADLPPort04, ADLPPort05, ADLPPort06, ADLPPort07,
ADLPPort08, ADLPPort09, ADLPPort10, ADLPPort11]>;

// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available
// until 5 cycles after the memory operand.
def : ReadAdvance<ReadAfterLd, 5>;
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