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[RISCV] Rename FeatureRVE to FeatureStdExtE. NFC #89174

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Merged
merged 1 commit into from
Apr 19, 2024
+15 −15
Merged

[RISCV] Rename FeatureRVE to FeatureStdExtE. NFC #89174

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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Expand Up @@ -83,7 +83,7 @@ class RISCVAsmParser : public MCTargetAsmParser {

SMLoc getLoc() const { return getParser().getTok().getLoc(); }
bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
bool isRVE() const { return getSTI().hasFeature(RISCV::FeatureRVE); }
bool isRVE() const { return getSTI().hasFeature(RISCV::FeatureStdExtE); }

RISCVTargetStreamer &getTargetStreamer() {
assert(getParser().getStreamer().getTargetStreamer() &&
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
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Expand Up @@ -64,7 +64,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureRVE);
bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);

if (RegNo >= 32 || (IsRVE && RegNo >= 16))
return MCDisassembler::Fail;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
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Expand Up @@ -40,7 +40,7 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
StringRef ABIName) {
auto TargetABI = getTargetABI(ABIName);
bool IsRV64 = TT.isArch64Bit();
bool IsRVE = FeatureBits[RISCV::FeatureRVE];
bool IsRVE = FeatureBits[RISCV::FeatureStdExtE];

if (!ABIName.empty() && TargetABI == ABI_Unknown) {
errs()
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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -16,6 +16,10 @@ def FeatureStdExtI
: SubtargetFeature<"i", "HasStdExtI", "true",
"'I' (Base Integer Instruction Set)">;

def FeatureStdExtE
: SubtargetFeature<"e", "HasStdExtE", "true",
"Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;

def FeatureStdExtZic64b
: SubtargetFeature<"zic64b", "HasStdExtZic64b", "true",
"'Zic64b' (Cache Block Size Is 64 Bytes)">;
Expand Down Expand Up @@ -1165,10 +1169,6 @@ def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
defvar RV32 = DefaultMode;
def RV64 : HwMode<"+64bit", [IsRV64]>;

def FeatureRVE
: SubtargetFeature<"e", "IsRVE", "true",
"Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;

def FeatureRelax
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
"Enable Linker relaxation.">;
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -18951,7 +18951,7 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
case CallingConv::RISCV_VectorCall:
break;
case CallingConv::GHC:
if (Subtarget.isRVE())
if (Subtarget.hasStdExtE())
report_fatal_error("GHC calling convention is not supported on RVE!");
if (!Subtarget.hasStdExtFOrZfinx() || !Subtarget.hasStdExtDOrZdinx())
report_fatal_error("GHC calling convention requires the (Zfinx/F) and "
Expand Down Expand Up @@ -19189,7 +19189,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());

if (CallConv == CallingConv::GHC) {
if (Subtarget.isRVE())
if (Subtarget.hasStdExtE())
report_fatal_error("GHC calling convention is not supported on RVE!");
ArgCCInfo.AnalyzeCallOperands(Outs, RISCV::CC_RISCV_GHC);
} else
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12 changes: 6 additions & 6 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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Expand Up @@ -65,10 +65,10 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
if (Subtarget.hasStdExtD())
return CSR_XLEN_F64_Interrupt_SaveList;
if (Subtarget.hasStdExtF())
return Subtarget.isRVE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
: CSR_XLEN_F32_Interrupt_SaveList;
return Subtarget.isRVE() ? CSR_Interrupt_RVE_SaveList
: CSR_Interrupt_SaveList;
return Subtarget.hasStdExtE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
: CSR_XLEN_F32_Interrupt_SaveList;
return Subtarget.hasStdExtE() ? CSR_Interrupt_RVE_SaveList
: CSR_Interrupt_SaveList;
}

bool HasVectorCSR =
Expand Down Expand Up @@ -126,7 +126,7 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, RISCV::DUMMY_REG_PAIR_WITH_X0);

// There are only 16 GPRs for RVE.
if (Subtarget.isRVE())
if (Subtarget.hasStdExtE())
for (MCPhysReg Reg = RISCV::X16; Reg <= RISCV::X31; Reg++)
markSuperRegs(Reserved, Reg);

Expand All @@ -145,7 +145,7 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, RISCV::VCIX_STATE);

if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
if (Subtarget.isRVE())
if (Subtarget.hasStdExtE())
report_fatal_error("Graal reserved registers do not exist in RVE");
markSuperRegs(Reserved, RISCV::X23);
markSuperRegs(Reserved, RISCV::X27);
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