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[DAG] SelectionDAG.computeKnownBits - add NSW/NUW flags support to ISD::SHL handling #89877

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Merged
merged 9 commits into from
May 2, 2024
Merged

[DAG] SelectionDAG.computeKnownBits - add NSW/NUW flags support to ISD::SHL handling #89877

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ea74bf2
feat: add NSW & NUW & ShAmtNonZero
zxc12523 Apr 24, 2024
c22ef9f
Merge branch 'llvm:main' into 89414
zxc12523 Apr 24, 2024
1b5d177
add new codegen
zxc12523 Apr 26, 2024
8578c44
create codegen test: pr89877.ll
zxc12523 Apr 26, 2024
addd9c0
Test individual nuw/nsu flags & Add expect fail to other .ll
zxc12523 Apr 29, 2024
ba07a98
Change Op.getNode()->Flags to Op->getFlags() & Remove XFail
zxc12523 Apr 30, 2024
2bd187b
Fix indentation in pr89877.ll
zxc12523 Apr 30, 2024
cb72268
Update fold-int-pow2-with-fmul-or-fdiv.ll & known-never-zero.ll
zxc12523 Apr 30, 2024
ae73713
fix newline in fold-int-pow2-with-fmul-or-fdiv.ll
zxc12523 May 1, 2024
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11 changes: 9 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3492,16 +3492,23 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
Known.Zero.setBitsFrom(1);
break;
}
case ISD::SHL:
case ISD::SHL: {
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
Known = KnownBits::shl(Known, Known2);

bool NUW = Op.getNode()->Flags.hasNoUnsignedWrap();
bool NSW = Op.getNode()->Flags.hasNoSignedWrap();

bool ShAmtNonZero = Known2.isNonZero();

Known = KnownBits::shl(Known, Known2, NUW, NSW, ShAmtNonZero);

// Minimum shift low bits are known zero.
if (const APInt *ShMinAmt =
getValidMinimumShiftAmountConstant(Op, DemandedElts))
Known.Zero.setLowBits(ShMinAmt->getZExtValue());
break;
}
case ISD::SRL:
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
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