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[DAG] Fold bitreverse(shl/srl(bitreverse(x),y)) -> srl/shl(x,y) #89897

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Merged
merged 1 commit into from
May 6, 2024
Merged

[DAG] Fold bitreverse(shl/srl(bitreverse(x),y)) -> srl/shl(x,y) #89897

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5 changes: 5 additions & 0 deletions llvm/include/llvm/CodeGen/SDPatternMatch.h
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Original file line number Diff line number Diff line change
Expand Up @@ -638,6 +638,11 @@ inline UnaryOpc_match<Opnd, true> m_ChainedUnaryOp(unsigned Opc,
return UnaryOpc_match<Opnd, true>(Opc, Op);
}

template <typename Opnd>
inline UnaryOpc_match<Opnd> m_BitReverse(const Opnd &Op) {
return UnaryOpc_match<Opnd>(ISD::BITREVERSE, Op);
}

template <typename Opnd> inline UnaryOpc_match<Opnd> m_ZExt(const Opnd &Op) {
return UnaryOpc_match<Opnd>(ISD::ZERO_EXTEND, Op);
}
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14 changes: 14 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -10960,9 +10960,23 @@ SDValue DAGCombiner::visitBITREVERSE(SDNode *N) {
// fold (bitreverse c1) -> c2
if (SDValue C = DAG.FoldConstantArithmetic(ISD::BITREVERSE, DL, VT, {N0}))
return C;

// fold (bitreverse (bitreverse x)) -> x
if (N0.getOpcode() == ISD::BITREVERSE)
return N0.getOperand(0);

SDValue X, Y;

// fold (bitreverse (lshr (bitreverse x), y)) -> (shl x, y)
if ((!LegalOperations || TLI.isOperationLegal(ISD::SHL, VT)) &&
sd_match(N, m_BitReverse(m_Srl(m_BitReverse(m_Value(X)), m_Value(Y)))))
return DAG.getNode(ISD::SHL, DL, VT, X, Y);

// fold (bitreverse (shl (bitreverse x), y)) -> (lshr x, y)
if ((!LegalOperations || TLI.isOperationLegal(ISD::SRL, VT)) &&
sd_match(N, m_BitReverse(m_Shl(m_BitReverse(m_Value(X)), m_Value(Y)))))
return DAG.getNode(ISD::SRL, DL, VT, X, Y);

return SDValue();
}

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139 changes: 27 additions & 112 deletions llvm/test/CodeGen/RISCV/bitreverse-shift.ll
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@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV32ZBKB
; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBKB
; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefixes=RV64ZBKB
; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBKB

; TODO: These tests can be optimised
; These tests can be optimised
; fold (bitreverse(srl (bitreverse c), x)) -> (shl c, x)
; fold (bitreverse(shl (bitreverse c), x)) -> (srl c, x)

Expand All @@ -14,51 +14,21 @@ declare i32 @llvm.bitreverse.i32(i32)
declare i64 @llvm.bitreverse.i64(i64)

define i8 @test_bitreverse_srli_bitreverse_i8(i8 %a) nounwind {
; RV32ZBKB-LABEL: test_bitreverse_srli_bitreverse_i8:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 27
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 24
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_srli_bitreverse_i8:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 59
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 56
; RV64ZBKB-NEXT: ret
; CHECK-LABEL: test_bitreverse_srli_bitreverse_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: ret
%1 = call i8 @llvm.bitreverse.i8(i8 %a)
%2 = lshr i8 %1, 3
%3 = call i8 @llvm.bitreverse.i8(i8 %2)
ret i8 %3
}

define i16 @test_bitreverse_srli_bitreverse_i16(i16 %a) nounwind {
; RV32ZBKB-LABEL: test_bitreverse_srli_bitreverse_i16:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 23
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 16
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_srli_bitreverse_i16:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 55
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 48
; RV64ZBKB-NEXT: ret
; CHECK-LABEL: test_bitreverse_srli_bitreverse_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a0, a0, 7
; CHECK-NEXT: ret
%1 = call i16 @llvm.bitreverse.i16(i16 %a)
%2 = lshr i16 %1, 7
%3 = call i16 @llvm.bitreverse.i16(i16 %2)
Expand All @@ -68,21 +38,12 @@ define i16 @test_bitreverse_srli_bitreverse_i16(i16 %a) nounwind {
define i32 @test_bitreverse_srli_bitreverse_i32(i32 %a) nounwind {
; RV32ZBKB-LABEL: test_bitreverse_srli_bitreverse_i32:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 15
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: slli a0, a0, 15
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_srli_bitreverse_i32:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 47
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: slliw a0, a0, 15
; RV64ZBKB-NEXT: ret
%1 = call i32 @llvm.bitreverse.i32(i32 %a)
%2 = lshr i32 %1, 15
Expand All @@ -93,21 +54,13 @@ define i32 @test_bitreverse_srli_bitreverse_i32(i32 %a) nounwind {
define i64 @test_bitreverse_srli_bitreverse_i64(i64 %a) nounwind {
; RV32ZBKB-LABEL: test_bitreverse_srli_bitreverse_i64:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 1
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a1, a0
; RV32ZBKB-NEXT: slli a1, a0, 1
; RV32ZBKB-NEXT: li a0, 0
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_srli_bitreverse_i64:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 33
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: slli a0, a0, 33
; RV64ZBKB-NEXT: ret
%1 = call i64 @llvm.bitreverse.i64(i64 %a)
%2 = lshr i64 %1, 33
Expand All @@ -118,24 +71,14 @@ define i64 @test_bitreverse_srli_bitreverse_i64(i64 %a) nounwind {
define i8 @test_bitreverse_shli_bitreverse_i8(i8 %a) nounwind {
; RV32ZBKB-LABEL: test_bitreverse_shli_bitreverse_i8:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 24
; RV32ZBKB-NEXT: slli a0, a0, 3
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 24
; RV32ZBKB-NEXT: slli a0, a0, 24
; RV32ZBKB-NEXT: srli a0, a0, 27
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_shli_bitreverse_i8:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 56
; RV64ZBKB-NEXT: slli a0, a0, 3
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 56
; RV64ZBKB-NEXT: slli a0, a0, 56
; RV64ZBKB-NEXT: srli a0, a0, 59
; RV64ZBKB-NEXT: ret
%1 = call i8 @llvm.bitreverse.i8(i8 %a)
%2 = shl i8 %1, 3
Expand All @@ -146,24 +89,14 @@ define i8 @test_bitreverse_shli_bitreverse_i8(i8 %a) nounwind {
define i16 @test_bitreverse_shli_bitreverse_i16(i16 %a) nounwind {
; RV32ZBKB-LABEL: test_bitreverse_shli_bitreverse_i16:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 16
; RV32ZBKB-NEXT: slli a0, a0, 7
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 16
; RV32ZBKB-NEXT: slli a0, a0, 16
; RV32ZBKB-NEXT: srli a0, a0, 23
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_shli_bitreverse_i16:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 48
; RV64ZBKB-NEXT: slli a0, a0, 7
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 48
; RV64ZBKB-NEXT: slli a0, a0, 48
; RV64ZBKB-NEXT: srli a0, a0, 55
; RV64ZBKB-NEXT: ret
%1 = call i16 @llvm.bitreverse.i16(i16 %a)
%2 = shl i16 %1, 7
Expand All @@ -174,22 +107,12 @@ define i16 @test_bitreverse_shli_bitreverse_i16(i16 %a) nounwind {
define i32 @test_bitreverse_shli_bitreverse_i32(i32 %a) nounwind {
; RV32ZBKB-LABEL: test_bitreverse_shli_bitreverse_i32:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: slli a0, a0, 15
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a0, 15
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_shli_bitreverse_i32:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: slli a0, a0, 15
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 32
; RV64ZBKB-NEXT: srliw a0, a0, 15
; RV64ZBKB-NEXT: ret
%1 = call i32 @llvm.bitreverse.i32(i32 %a)
%2 = shl i32 %1, 15
Expand All @@ -200,21 +123,13 @@ define i32 @test_bitreverse_shli_bitreverse_i32(i32 %a) nounwind {
define i64 @test_bitreverse_shli_bitreverse_i64(i64 %a) nounwind {
; RV32ZBKB-LABEL: test_bitreverse_shli_bitreverse_i64:
; RV32ZBKB: # %bb.0:
; RV32ZBKB-NEXT: rev8 a0, a1
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: slli a0, a0, 1
; RV32ZBKB-NEXT: rev8 a0, a0
; RV32ZBKB-NEXT: brev8 a0, a0
; RV32ZBKB-NEXT: srli a0, a1, 1
; RV32ZBKB-NEXT: li a1, 0
; RV32ZBKB-NEXT: ret
;
; RV64ZBKB-LABEL: test_bitreverse_shli_bitreverse_i64:
; RV64ZBKB: # %bb.0:
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: slli a0, a0, 33
; RV64ZBKB-NEXT: rev8 a0, a0
; RV64ZBKB-NEXT: brev8 a0, a0
; RV64ZBKB-NEXT: srli a0, a0, 33
; RV64ZBKB-NEXT: ret
%1 = call i64 @llvm.bitreverse.i64(i64 %a)
%2 = shl i64 %1, 33
Expand Down
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