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[RISCV][ISel] Eliminate andi rd, rs1, -1 instructions #89976

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Merged
merged 3 commits into from
Apr 25, 2024
Merged

[RISCV][ISel] Eliminate andi rd, rs1, -1 instructions #89976

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d78c9d6
[RISCV][ISel] Add pre-commit tests. NFC.
dtcxzyw Apr 24, 2024
23cec61
[RISCV][ISel] Eliminate `andi rd, rs1, -1` instructions
dtcxzyw Apr 24, 2024
5f42f80
[RISCV][ISel] Remove dead FIXMEs. NFC.
dtcxzyw Apr 24, 2024
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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1813,6 +1813,8 @@ def : Pat<(binop_allwusers<srl> (sext_inreg GPR:$rs1, i32), uimm5:$shamt),

// Use binop_allwusers to recover immediates that may have been broken by
// SimplifyDemandedBits.
def : Pat<(binop_allwusers<and> GPR:$rs1, 0xffffffff),
(COPY GPR:$rs1)>;
def : Pat<(binop_allwusers<and> GPR:$rs1, u32simm12:$imm),
(ANDI GPR:$rs1, u32simm12:$imm)>;

Expand Down
6 changes: 0 additions & 6 deletions llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll
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Expand Up @@ -634,7 +634,6 @@ define i64 @zext_mul288(i32 signext %a) {
}

; We can't use slli.uw becaues the shift amount is more than 31.
; FIXME: The zext.w is unneeded.
define i64 @zext_mul12884901888(i32 signext %a) {
; RV64I-LABEL: zext_mul12884901888:
; RV64I: # %bb.0:
Expand All @@ -647,7 +646,6 @@ define i64 @zext_mul12884901888(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul12884901888:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
Expand All @@ -657,7 +655,6 @@ define i64 @zext_mul12884901888(i32 signext %a) {
}

; We can't use slli.uw becaues the shift amount is more than 31.
; FIXME: The zext.w is unneeded.
define i64 @zext_mul21474836480(i32 signext %a) {
; RV64I-LABEL: zext_mul21474836480:
; RV64I: # %bb.0:
Expand All @@ -670,7 +667,6 @@ define i64 @zext_mul21474836480(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul21474836480:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
Expand All @@ -680,7 +676,6 @@ define i64 @zext_mul21474836480(i32 signext %a) {
}

; We can't use slli.uw becaues the shift amount is more than 31.
; FIXME: The zext.w is unneeded.
define i64 @zext_mul38654705664(i32 signext %a) {
; RV64I-LABEL: zext_mul38654705664:
; RV64I: # %bb.0:
Expand All @@ -693,7 +688,6 @@ define i64 @zext_mul38654705664(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul38654705664:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
Expand Down
58 changes: 26 additions & 32 deletions llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll
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Expand Up @@ -102,11 +102,10 @@ declare i32 @llvm.fshl.i32(i32, i32, i32)
define signext i32 @rol_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: rol_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a2, a1, -1
; RV64I-NEXT: sllw a1, a0, a1
; RV64I-NEXT: negw a2, a2
; RV64I-NEXT: srlw a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: sllw a2, a0, a1
; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
; RV64ZBB-ZBKB-LABEL: rol_i32:
Expand All @@ -121,11 +120,10 @@ define signext i32 @rol_i32(i32 signext %a, i32 signext %b) nounwind {
define void @rol_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind {
; RV64I-LABEL: rol_i32_nosext:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a3, a1, -1
; RV64I-NEXT: sllw a1, a0, a1
; RV64I-NEXT: negw a3, a3
; RV64I-NEXT: srlw a0, a0, a3
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: sllw a3, a0, a1
; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: srlw a0, a0, a1
; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret
;
Expand All @@ -142,12 +140,11 @@ define void @rol_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind {
define signext i32 @rol_i32_neg_constant_rhs(i32 signext %a) nounwind {
; RV64I-LABEL: rol_i32_neg_constant_rhs:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a0, -1
; RV64I-NEXT: li a2, -2
; RV64I-NEXT: sllw a0, a2, a0
; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: srlw a1, a2, a1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: li a1, -2
; RV64I-NEXT: sllw a2, a1, a0
; RV64I-NEXT: negw a0, a0
; RV64I-NEXT: srlw a0, a1, a0
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
; RV64ZBB-ZBKB-LABEL: rol_i32_neg_constant_rhs:
Expand Down Expand Up @@ -183,11 +180,10 @@ declare i32 @llvm.fshr.i32(i32, i32, i32)
define signext i32 @ror_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: ror_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a2, a1, -1
; RV64I-NEXT: srlw a1, a0, a1
; RV64I-NEXT: negw a2, a2
; RV64I-NEXT: sllw a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srlw a2, a0, a1
; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
; RV64ZBB-ZBKB-LABEL: ror_i32:
Expand All @@ -202,11 +198,10 @@ define signext i32 @ror_i32(i32 signext %a, i32 signext %b) nounwind {
define void @ror_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind {
; RV64I-LABEL: ror_i32_nosext:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a3, a1, -1
; RV64I-NEXT: srlw a1, a0, a1
; RV64I-NEXT: negw a3, a3
; RV64I-NEXT: sllw a0, a0, a3
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srlw a3, a0, a1
; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: or a0, a3, a0
; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret
;
Expand All @@ -223,12 +218,11 @@ define void @ror_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind {
define signext i32 @ror_i32_neg_constant_rhs(i32 signext %a) nounwind {
; RV64I-LABEL: ror_i32_neg_constant_rhs:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a1, a0, -1
; RV64I-NEXT: li a2, -2
; RV64I-NEXT: srlw a0, a2, a0
; RV64I-NEXT: negw a1, a1
; RV64I-NEXT: sllw a1, a2, a1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: li a1, -2
; RV64I-NEXT: srlw a2, a1, a0
; RV64I-NEXT: negw a0, a0
; RV64I-NEXT: sllw a0, a1, a0
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ret
;
; RV64ZBB-ZBKB-LABEL: ror_i32_neg_constant_rhs:
Expand Down
14 changes: 14 additions & 0 deletions llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll
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Expand Up @@ -192,3 +192,17 @@ entry:
%or = or i32 %and, 255
ret i32 %or
}

define i64 @and_allones(i32 signext %x) {
; CHECK-LABEL: and_allones:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: li a1, 1
; CHECK-NEXT: sll a0, a1, a0
; CHECK-NEXT: ret
entry:
%y = zext i32 %x to i64
%shamt = add nsw i64 %y, -1
%ret = shl i64 1, %shamt
ret i64 %ret
}
6 changes: 0 additions & 6 deletions llvm/test/CodeGen/RISCV/rv64zba.ll
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Expand Up @@ -851,7 +851,6 @@ define i64 @zext_mul288(i32 signext %a) {
}

; We can't use slli.uw becaues the shift amount is more than 31.
; FIXME: The zext.w is unneeded.
define i64 @zext_mul12884901888(i32 signext %a) {
; RV64I-LABEL: zext_mul12884901888:
; RV64I: # %bb.0:
Expand All @@ -864,7 +863,6 @@ define i64 @zext_mul12884901888(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul12884901888:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh1add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
Expand All @@ -874,7 +872,6 @@ define i64 @zext_mul12884901888(i32 signext %a) {
}

; We can't use slli.uw becaues the shift amount is more than 31.
; FIXME: The zext.w is unneeded.
define i64 @zext_mul21474836480(i32 signext %a) {
; RV64I-LABEL: zext_mul21474836480:
; RV64I: # %bb.0:
Expand All @@ -887,7 +884,6 @@ define i64 @zext_mul21474836480(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul21474836480:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh2add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
Expand All @@ -897,7 +893,6 @@ define i64 @zext_mul21474836480(i32 signext %a) {
}

; We can't use slli.uw becaues the shift amount is more than 31.
; FIXME: The zext.w is unneeded.
define i64 @zext_mul38654705664(i32 signext %a) {
; RV64I-LABEL: zext_mul38654705664:
; RV64I: # %bb.0:
Expand All @@ -910,7 +905,6 @@ define i64 @zext_mul38654705664(i32 signext %a) {
;
; RV64ZBA-LABEL: zext_mul38654705664:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: andi a0, a0, -1
; RV64ZBA-NEXT: sh3add a0, a0, a0
; RV64ZBA-NEXT: slli a0, a0, 32
; RV64ZBA-NEXT: ret
Expand Down
104 changes: 32 additions & 72 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
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Expand Up @@ -574,24 +574,14 @@ define signext i32 @vpreduce_add_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m
declare i32 @llvm.vp.reduce.umax.v2i32(i32, <2 x i32>, <2 x i1>, i32)

define signext i32 @vpreduce_umax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umax_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: andi a0, a0, -1
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vmv.s.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
; CHECK-LABEL: vpreduce_umax_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
}
Expand All @@ -614,24 +604,14 @@ define signext i32 @vpreduce_smax_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %
declare i32 @llvm.vp.reduce.umin.v2i32(i32, <2 x i32>, <2 x i1>, i32)

define signext i32 @vpreduce_umin_v2i32(i32 signext %s, <2 x i32> %v, <2 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umin_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: andi a0, a0, -1
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vmv.s.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
; CHECK-LABEL: vpreduce_umin_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.v2i32(i32 %s, <2 x i32> %v, <2 x i1> %m, i32 %evl)
ret i32 %r
}
Expand Down Expand Up @@ -714,24 +694,14 @@ define signext i32 @vpreduce_add_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m
declare i32 @llvm.vp.reduce.umax.v4i32(i32, <4 x i32>, <4 x i1>, i32)

define signext i32 @vpreduce_umax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umax_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umax_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: andi a0, a0, -1
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vmv.s.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t
; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
; CHECK-LABEL: vpreduce_umax_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t
; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
}
Expand All @@ -754,24 +724,14 @@ define signext i32 @vpreduce_smax_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %
declare i32 @llvm.vp.reduce.umin.v4i32(i32, <4 x i32>, <4 x i1>, i32)

define signext i32 @vpreduce_umin_v4i32(i32 signext %s, <4 x i32> %v, <4 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umin_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT: vmv.s.x v9, a0
; RV32-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t
; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_umin_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: andi a0, a0, -1
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vmv.s.x v9, a0
; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t
; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret
; CHECK-LABEL: vpreduce_umin_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t
; CHECK-NEXT: vmv.x.s a0, v9
; CHECK-NEXT: ret
%r = call i32 @llvm.vp.reduce.umin.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
ret i32 %r
}
Expand Down
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