Skip to content

[AArch64][GlobalISel] Select G_ICMP Zero Instruction #90054

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
May 14, 2024
Merged

[AArch64][GlobalISel] Select G_ICMP Zero Instruction #90054

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
46 changes: 46 additions & 0 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5449,6 +5449,52 @@ defm : SelectSetCCSwapOperands<setle, "CMGE">;
defm : SelectSetCCSwapOperands<setult, "CMHI">;
defm : SelectSetCCSwapOperands<setule, "CMHS">;

multiclass SelectSetCCZeroRHS<PatFrags InFrag, string INST> {
def : Pat<(v8i8 (InFrag (v8i8 V64:$Rn), immAllZerosV)),
(v8i8 (!cast<Instruction>(INST # v8i8rz) (v8i8 V64:$Rn)))>;
def : Pat<(v16i8 (InFrag (v16i8 V128:$Rn), immAllZerosV)),
(v16i8 (!cast<Instruction>(INST # v16i8rz) (v16i8 V128:$Rn)))>;
def : Pat<(v4i16 (InFrag (v4i16 V64:$Rn), immAllZerosV)),
(v4i16 (!cast<Instruction>(INST # v4i16rz) (v4i16 V64:$Rn)))>;
def : Pat<(v8i16 (InFrag (v8i16 V128:$Rn), immAllZerosV)),
(v8i16 (!cast<Instruction>(INST # v8i16rz) (v8i16 V128:$Rn)))>;
def : Pat<(v2i32 (InFrag (v2i32 V64:$Rn), immAllZerosV)),
(v2i32 (!cast<Instruction>(INST # v2i32rz) (v2i32 V64:$Rn)))>;
def : Pat<(v4i32 (InFrag (v4i32 V128:$Rn), immAllZerosV)),
(v4i32 (!cast<Instruction>(INST # v4i32rz) (v4i32 V128:$Rn)))>;
def : Pat<(v2i64 (InFrag (v2i64 V128:$Rn), immAllZerosV)),
(v2i64 (!cast<Instruction>(INST # v2i64rz) (v2i64 V128:$Rn)))>;
}

defm : SelectSetCCZeroRHS<seteq, "CMEQ">;
defm : SelectSetCCZeroRHS<setgt, "CMGT">;
defm : SelectSetCCZeroRHS<setge, "CMGE">;
defm : SelectSetCCZeroRHS<setlt, "CMLT">;
defm : SelectSetCCZeroRHS<setle, "CMLE">;

multiclass SelectSetCCZeroLHS<PatFrags InFrag, string INST> {
def : Pat<(v8i8 (InFrag immAllZerosV, (v8i8 V64:$Rn))),
(v8i8 (!cast<Instruction>(INST # v8i8rz) (v8i8 V64:$Rn)))>;
def : Pat<(v16i8 (InFrag immAllZerosV, (v16i8 V128:$Rn))),
(v16i8 (!cast<Instruction>(INST # v16i8rz) (v16i8 V128:$Rn)))>;
def : Pat<(v4i16 (InFrag immAllZerosV, (v4i16 V64:$Rn))),
(v4i16 (!cast<Instruction>(INST # v4i16rz) (v4i16 V64:$Rn)))>;
def : Pat<(v8i16 (InFrag immAllZerosV, (v8i16 V128:$Rn))),
(v8i16 (!cast<Instruction>(INST # v8i16rz) (v8i16 V128:$Rn)))>;
def : Pat<(v2i32 (InFrag immAllZerosV, (v2i32 V64:$Rn))),
(v2i32 (!cast<Instruction>(INST # v2i32rz) (v2i32 V64:$Rn)))>;
def : Pat<(v4i32 (InFrag immAllZerosV, (v4i32 V128:$Rn))),
(v4i32 (!cast<Instruction>(INST # v4i32rz) (v4i32 V128:$Rn)))>;
def : Pat<(v2i64 (InFrag immAllZerosV, (v2i64 V128:$Rn))),
(v2i64 (!cast<Instruction>(INST # v2i64rz) (v2i64 V128:$Rn)))>;
}

defm : SelectSetCCZeroLHS<seteq, "CMEQ">;
defm : SelectSetCCZeroLHS<setgt, "CMLT">;
defm : SelectSetCCZeroLHS<setge, "CMLE">;
defm : SelectSetCCZeroLHS<setlt, "CMGT">;
defm : SelectSetCCZeroLHS<setle, "CMGE">;

let Predicates = [HasNEON] in {
def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
(ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
Expand Down
25 changes: 12 additions & 13 deletions llvm/test/CodeGen/AArch64/aarch64-addv.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -94,20 +94,19 @@ define i32 @oversized_ADDV_256(ptr noalias nocapture readonly %arg1, ptr noalias
;
; GISEL-LABEL: oversized_ADDV_256:
; GISEL: // %bb.0: // %entry
; GISEL-NEXT: ldr d1, [x0]
; GISEL-NEXT: ldr d2, [x1]
; GISEL-NEXT: movi v0.2d, #0000000000000000
; GISEL-NEXT: ldr d0, [x0]
; GISEL-NEXT: ldr d1, [x1]
; GISEL-NEXT: ushll v0.8h, v0.8b, #0
; GISEL-NEXT: ushll v1.8h, v1.8b, #0
; GISEL-NEXT: ushll v2.8h, v2.8b, #0
; GISEL-NEXT: usubl v3.4s, v1.4h, v2.4h
; GISEL-NEXT: usubl2 v1.4s, v1.8h, v2.8h
; GISEL-NEXT: cmgt v2.4s, v0.4s, v3.4s
; GISEL-NEXT: cmgt v0.4s, v0.4s, v1.4s
; GISEL-NEXT: neg v4.4s, v3.4s
; GISEL-NEXT: neg v5.4s, v1.4s
; GISEL-NEXT: bsl v2.16b, v4.16b, v3.16b
; GISEL-NEXT: bsl v0.16b, v5.16b, v1.16b
; GISEL-NEXT: add v0.4s, v2.4s, v0.4s
; GISEL-NEXT: usubl v2.4s, v0.4h, v1.4h
; GISEL-NEXT: usubl2 v0.4s, v0.8h, v1.8h
; GISEL-NEXT: cmlt v1.4s, v2.4s, #0
; GISEL-NEXT: cmlt v3.4s, v0.4s, #0
; GISEL-NEXT: neg v4.4s, v2.4s
; GISEL-NEXT: neg v5.4s, v0.4s
; GISEL-NEXT: bsl v1.16b, v4.16b, v2.16b
; GISEL-NEXT: bit v0.16b, v5.16b, v3.16b
; GISEL-NEXT: add v0.4s, v1.4s, v0.4s
; GISEL-NEXT: addv s0, v0.4s
; GISEL-NEXT: fmov w0, s0
; GISEL-NEXT: ret
Expand Down
Loading
Loading