[RISCV][TableGen] Get right experimental extension name

[wangpc-pp]

We should remove the experimental- prefix when printing march
string.

We didn't meet this problem because there is no processor containing
experimental extensions.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Pengcheng Wang (wangpc-pp)

Changes

We should remove the experimental- prefix when printing march
string.

We didn't meet this problem because there is no processor containing
experimental extensions.

---

Full diff: https://github.com/llvm/llvm-project/pull/90185.diff

2 Files Affected:

• (modified) llvm/test/TableGen/riscv-target-def.td (+4-2)
• (modified) llvm/utils/TableGen/RISCVTargetDefEmitter.cpp (+1-1)

diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index b23c7e4d40198b..175b68f9f8bad7 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -83,6 +83,7 @@ def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
                                        FeatureStdExtI,
                                        FeatureStdExtZifencei,
                                        FeatureStdExtZicsr,
+                                       FeatureStdExtZidummy,
                                        FeatureDummy]>;
 def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
                                       NoSchedModel,
@@ -90,6 +91,7 @@ def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
                                        FeatureStdExtI,
                                        FeatureStdExtZifencei,
                                        FeatureStdExtZicsr,
+                                       FeatureStdExtZidummy,
                                        FeatureDummy]>;
 def ROCKET : RISCVTuneProcessorModel<"rocket",
                                      NoSchedModel>;
@@ -127,8 +129,8 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
 
 // CHECK:      PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0)
 // CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0)
-// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zifencei2p0"}, 0)
-// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zifencei2p0"}, 0)
+// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0)
+// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0)
 
 // CHECK: #undef PROC
 
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 217b531dcfd394..4580a0ab12669c 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -119,7 +119,7 @@ static void printMArch(raw_ostream &OS, const Record &Rec) {
 
   // Convert features to FeatureVector.
   for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
-    StringRef FeatureName = Feature->getValueAsString("Name");
+    StringRef FeatureName = getExtensionName(Feature);
     if (Feature->isSubClassOf("RISCVExtension")) {
       unsigned Major = Feature->getValueAsInt("MajorVersion");
       unsigned Minor = Feature->getValueAsInt("MinorVersion");

[asb]

Alternatively, should we reject processor definitions that have experimental extensions? Are we sure that processors with experimental extensions interact properly with the gating of experimental extensions behind -menable-experimental-extensions for user facing tools like clang?

[wangpc-pp]

Alternatively, should we reject processor definitions that have experimental extensions? Are we sure that processors with experimental extensions interact properly with the gating of experimental extensions behind -menable-experimental-extensions for user facing tools like clang?

I found this issue (if it is an issue) in #90187 as Ssnpm, which is a mandatory extension in RVA23S64, is an experimental extension.
I think we shouldn't have experimental extensions in processor definitions, but there are some intermediate periods that we don't have other choices. For example, Zicond is experimental in LLVM 17, but it hasn't been changed for a long time and we moved it out from experimental in LLVM 18. For downstreams, there is a period of half a year that experimental extensions exist in processor definitions (these definitions are just used for pre-silicon tests).
And yes, of course, -menable-experimental-extensions should be specified along with -mcpu in this situation.

[topperc]

LGTM

[asb]

Ok, thanks for answering my question. LGTM.