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[RISCV] Split RISCVDisassembler::getInstruction into a 16-bit and 32-bit version. #90254

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Merged
merged 1 commit into from
Apr 26, 2024
Merged

[RISCV] Split RISCVDisassembler::getInstruction into a 16-bit and 32-bit version. #90254

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218 changes: 119 additions & 99 deletions llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,13 @@ class RISCVDisassembler : public MCDisassembler {

private:
void addSPOperands(MCInst &MI) const;

DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &CStream) const;
DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address,
raw_ostream &CStream) const;
};
} // end anonymous namespace

Expand Down Expand Up @@ -502,21 +509,13 @@ void RISCVDisassembler::addSPOperands(MCInst &MI) const {
MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
}

DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes,
uint64_t Address,
raw_ostream &CS) const {
// TODO: This will need modification when supporting instruction set
// extensions with instructions > 32-bits (up to 176 bits wide).
uint32_t Insn;
DecodeStatus Result;

#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, \
DESC, ADDITIONAL_OPERATION) \
do { \
if (FEATURE_CHECKS) { \
LLVM_DEBUG(dbgs() << "Trying " DESC ":\n"); \
Result = decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
DecodeStatus Result = \
decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \
if (Result != MCDisassembler::Fail) { \
ADDITIONAL_OPERATION; \
return Result; \
Expand All @@ -532,104 +531,111 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
#define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC) \
TRY_TO_DECODE(STI.hasFeature(FEATURE), DECODER_TABLE, DESC)

// It's a 32 bit instruction if bit 0 and 1 are 1.
if ((Bytes[0] & 0x3) == 0x3) {
if (Bytes.size() < 4) {
Size = 0;
return MCDisassembler::Fail;
}
Size = 4;

Insn = support::endian::read32le(Bytes.data());

TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
!STI.hasFeature(RISCV::Feature64Bit),
DecoderTableRV32Zdinx32,
"RV32Zdinx table (Double in Integer and rv32)");
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) &&
!STI.hasFeature(RISCV::Feature64Bit),
DecoderTableRV32Zacas32,
"RV32Zacas table (Compare-And-Swap and rv32)");
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
"RVZfinx table (Float in Integer)");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
DecoderTableXVentana32, "Ventana custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
"XTHeadBa custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
"XTHeadBb custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
"XTHeadBs custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
DecoderTableXTHeadCondMov32,
"XTHeadCondMov custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
"XTHeadCmo custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
DecoderTableXTHeadFMemIdx32,
"XTHeadFMemIdx custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
"XTHeadMac custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
DecoderTableXTHeadMemIdx32,
"XTHeadMemIdx custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
DecoderTableXTHeadMemPair32,
"XTHeadMemPair custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
DecoderTableXTHeadSync32,
"XTHeadSync custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32,
"XTHeadVdot custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
"SiFive VCIX custom opcode table");
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
"SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
"SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
"SiFive Matrix Multiplication Instruction opcode table");
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
DecoderTableXSiFivecdiscarddlone32,
"SiFive sf.cdiscard.d.l1 custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
DecoderTableXSiFivecflushdlone32,
"SiFive sf.cflush.d.l1 custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
"SiFive sf.cease custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
DecoderTableXCVbitmanip32,
"CORE-V Bit Manipulation custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
"CORE-V Event load custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
"CORE-V MAC custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
"CORE-V MEM custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
"CORE-V ALU custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
"CORE-V SIMD extensions custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
"CORE-V Immediate Branching custom opcode table");
TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");

DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes,
uint64_t Address,
raw_ostream &CS) const {
if (Bytes.size() < 4) {
Size = 0;
return MCDisassembler::Fail;
}
Size = 4;

uint32_t Insn = support::endian::read32le(Bytes.data());

TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) &&
!STI.hasFeature(RISCV::Feature64Bit),
DecoderTableRV32Zdinx32,
"RV32Zdinx table (Double in Integer and rv32)");
TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) &&
!STI.hasFeature(RISCV::Feature64Bit),
DecoderTableRV32Zacas32,
"RV32Zacas table (Compare-And-Swap and rv32)");
TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32,
"RVZfinx table (Float in Integer)");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps,
DecoderTableXVentana32, "Ventana custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32,
"XTHeadBa custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32,
"XTHeadBb custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32,
"XTHeadBs custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov,
DecoderTableXTHeadCondMov32,
"XTHeadCondMov custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32,
"XTHeadCmo custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx,
DecoderTableXTHeadFMemIdx32,
"XTHeadFMemIdx custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32,
"XTHeadMac custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx,
DecoderTableXTHeadMemIdx32,
"XTHeadMemIdx custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair,
DecoderTableXTHeadMemPair32,
"XTHeadMemPair custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync,
DecoderTableXTHeadSync32,
"XTHeadSync custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot,
DecoderTableXTHeadVdot32,
"XTHeadVdot custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32,
"SiFive VCIX custom opcode table");
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32,
"SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32,
"SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32,
"SiFive Matrix Multiplication Instruction opcode table");
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32,
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone,
DecoderTableXSiFivecdiscarddlone32,
"SiFive sf.cdiscard.d.l1 custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone,
DecoderTableXSiFivecflushdlone32,
"SiFive sf.cflush.d.l1 custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32,
"SiFive sf.cease custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip,
DecoderTableXCVbitmanip32,
"CORE-V Bit Manipulation custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32,
"CORE-V Event load custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
"CORE-V MAC custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32,
"CORE-V MEM custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
"CORE-V ALU custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32,
"CORE-V SIMD extensions custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
"CORE-V Immediate Branching custom opcode table");
TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");

return MCDisassembler::Fail;
}

DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes,
uint64_t Address,
raw_ostream &CS) const {
if (Bytes.size() < 2) {
Size = 0;
return MCDisassembler::Fail;
}
Size = 2;

Insn = support::endian::read16le(Bytes.data());
uint32_t Insn = support::endian::read16le(Bytes.data());
TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit),
DecoderTableRISCV32Only_16,
"RISCV32Only_16 table (16-bit Instruction)");
Expand All @@ -645,3 +651,17 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,

return MCDisassembler::Fail;
}

DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes,
uint64_t Address,
raw_ostream &CS) const {
// TODO: This will need modification when supporting instruction set
// extensions with instructions > 32-bits (up to 176 bits wide).

// It's a 32 bit instruction if bit 0 and 1 are 1.
if ((Bytes[0] & 0x3) == 0x3)
return getInstruction32(MI, Size, Bytes, Address, CS);

return getInstruction16(MI, Size, Bytes, Address, CS);
}