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Add clarifying parenthesis around non-trivial conditions in ternary expressions. #90391

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Merged
merged 2 commits into from
May 4, 2024
Merged

Add clarifying parenthesis around non-trivial conditions in ternary expressions. #90391

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54c6c6b
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3804: lacking () for c…
luolent Apr 27, 2024
9d71a76
Merge branch 'main' into issue_85868
luolent May 3, 2024
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2 changes: 1 addition & 1 deletion clang/lib/Basic/Targets/AMDGPU.cpp
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Expand Up @@ -232,7 +232,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple,

HasLegalHalfType = true;
HasFloat16 = true;
WavefrontSize = GPUFeatures & llvm::AMDGPU::FEATURE_WAVE32 ? 32 : 64;
WavefrontSize = (GPUFeatures & llvm::AMDGPU::FEATURE_WAVE32) ? 32 : 64;
AllowAMDGPUUnsafeFPAtomics = Opts.AllowAMDGPUUnsafeFPAtomics;

// Set pointer width and alignment for the generic address space.
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2 changes: 1 addition & 1 deletion compiler-rt/lib/xray/xray_utils.h
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Expand Up @@ -61,7 +61,7 @@ constexpr size_t gcd(size_t a, size_t b) {
constexpr size_t lcm(size_t a, size_t b) { return a * b / gcd(a, b); }

constexpr size_t nearest_boundary(size_t number, size_t multiple) {
return multiple * ((number / multiple) + (number % multiple ? 1 : 0));
return multiple * ((number / multiple) + ((number % multiple) ? 1 : 0));
}

constexpr size_t next_pow2_helper(size_t num, size_t acc) {
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20 changes: 10 additions & 10 deletions libc/src/__support/FPUtil/aarch64/FEnvImpl.h
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Expand Up @@ -53,19 +53,19 @@ struct FEnv {
static constexpr uint32_t ExceptionControlFlagsBitPosition = 8;

LIBC_INLINE static uint32_t getStatusValueForExcept(int excepts) {
return (excepts & FE_INVALID ? INVALID : 0) |
(excepts & FE_DIVBYZERO ? DIVBYZERO : 0) |
(excepts & FE_OVERFLOW ? OVERFLOW : 0) |
(excepts & FE_UNDERFLOW ? UNDERFLOW : 0) |
(excepts & FE_INEXACT ? INEXACT : 0);
return ((excepts & FE_INVALID) ? INVALID : 0) |
((excepts & FE_DIVBYZERO) ? DIVBYZERO : 0) |
((excepts & FE_OVERFLOW) ? OVERFLOW : 0) |
((excepts & FE_UNDERFLOW) ? UNDERFLOW : 0) |
((excepts & FE_INEXACT) ? INEXACT : 0);
}

LIBC_INLINE static int exceptionStatusToMacro(uint32_t status) {
return (status & INVALID ? FE_INVALID : 0) |
(status & DIVBYZERO ? FE_DIVBYZERO : 0) |
(status & OVERFLOW ? FE_OVERFLOW : 0) |
(status & UNDERFLOW ? FE_UNDERFLOW : 0) |
(status & INEXACT ? FE_INEXACT : 0);
return ((status & INVALID) ? FE_INVALID : 0) |
((status & DIVBYZERO) ? FE_DIVBYZERO : 0) |
((status & OVERFLOW) ? FE_OVERFLOW : 0) |
((status & UNDERFLOW) ? FE_UNDERFLOW : 0) |
((status & INEXACT) ? FE_INEXACT : 0);
}

static uint32_t getControlWord() {
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48 changes: 24 additions & 24 deletions libc/src/__support/FPUtil/aarch64/fenv_darwin_impl.h
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Expand Up @@ -63,39 +63,39 @@ struct FEnv {
// located in a different place from FE_FLUSHTOZERO status bit relative to
// the other exceptions.
LIBC_INLINE static uint32_t exception_value_from_status(int status) {
return (status & FE_INVALID ? EX_INVALID : 0) |
(status & FE_DIVBYZERO ? EX_DIVBYZERO : 0) |
(status & FE_OVERFLOW ? EX_OVERFLOW : 0) |
(status & FE_UNDERFLOW ? EX_UNDERFLOW : 0) |
(status & FE_INEXACT ? EX_INEXACT : 0) |
(status & FE_FLUSHTOZERO ? EX_FLUSHTOZERO : 0);
return ((status & FE_INVALID) ? EX_INVALID : 0) |
((status & FE_DIVBYZERO) ? EX_DIVBYZERO : 0) |
((status & FE_OVERFLOW) ? EX_OVERFLOW : 0) |
((status & FE_UNDERFLOW) ? EX_UNDERFLOW : 0) |
((status & FE_INEXACT) ? EX_INEXACT : 0) |
((status & FE_FLUSHTOZERO) ? EX_FLUSHTOZERO : 0);
}

LIBC_INLINE static uint32_t exception_value_from_control(int control) {
return (control & __fpcr_trap_invalid ? EX_INVALID : 0) |
(control & __fpcr_trap_divbyzero ? EX_DIVBYZERO : 0) |
(control & __fpcr_trap_overflow ? EX_OVERFLOW : 0) |
(control & __fpcr_trap_underflow ? EX_UNDERFLOW : 0) |
(control & __fpcr_trap_inexact ? EX_INEXACT : 0) |
(control & __fpcr_flush_to_zero ? EX_FLUSHTOZERO : 0);
return ((control & __fpcr_trap_invalid) ? EX_INVALID : 0) |
((control & __fpcr_trap_divbyzero) ? EX_DIVBYZERO : 0) |
((control & __fpcr_trap_overflow) ? EX_OVERFLOW : 0) |
((control & __fpcr_trap_underflow) ? EX_UNDERFLOW : 0) |
((control & __fpcr_trap_inexact) ? EX_INEXACT : 0) |
((control & __fpcr_flush_to_zero) ? EX_FLUSHTOZERO : 0);
}

LIBC_INLINE static int exception_value_to_status(uint32_t excepts) {
return (excepts & EX_INVALID ? FE_INVALID : 0) |
(excepts & EX_DIVBYZERO ? FE_DIVBYZERO : 0) |
(excepts & EX_OVERFLOW ? FE_OVERFLOW : 0) |
(excepts & EX_UNDERFLOW ? FE_UNDERFLOW : 0) |
(excepts & EX_INEXACT ? FE_INEXACT : 0) |
(excepts & EX_FLUSHTOZERO ? FE_FLUSHTOZERO : 0);
return ((excepts & EX_INVALID) ? FE_INVALID : 0) |
((excepts & EX_DIVBYZERO) ? FE_DIVBYZERO : 0) |
((excepts & EX_OVERFLOW) ? FE_OVERFLOW : 0) |
((excepts & EX_UNDERFLOW) ? FE_UNDERFLOW : 0) |
((excepts & EX_INEXACT) ? FE_INEXACT : 0) |
((excepts & EX_FLUSHTOZERO) ? FE_FLUSHTOZERO : 0);
}

LIBC_INLINE static int exception_value_to_control(uint32_t excepts) {
return (excepts & EX_INVALID ? __fpcr_trap_invalid : 0) |
(excepts & EX_DIVBYZERO ? __fpcr_trap_divbyzero : 0) |
(excepts & EX_OVERFLOW ? __fpcr_trap_overflow : 0) |
(excepts & EX_UNDERFLOW ? __fpcr_trap_underflow : 0) |
(excepts & EX_INEXACT ? __fpcr_trap_inexact : 0) |
(excepts & EX_FLUSHTOZERO ? __fpcr_flush_to_zero : 0);
return ((excepts & EX_INVALID) ? __fpcr_trap_invalid : 0) |
((excepts & EX_DIVBYZERO) ? __fpcr_trap_divbyzero : 0) |
((excepts & EX_OVERFLOW) ? __fpcr_trap_overflow : 0) |
((excepts & EX_UNDERFLOW) ? __fpcr_trap_underflow : 0) |
((excepts & EX_INEXACT) ? __fpcr_trap_inexact : 0) |
((excepts & EX_FLUSHTOZERO) ? __fpcr_flush_to_zero : 0);
}

LIBC_INLINE static uint32_t get_control_word() { return __arm_rsr("fpcr"); }
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40 changes: 20 additions & 20 deletions libc/src/__support/FPUtil/arm/FEnvImpl.h
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Expand Up @@ -50,35 +50,35 @@ struct FEnv {
}

LIBC_INLINE static int exception_enable_bits_to_macro(uint32_t status) {
return (status & INVALID_ENABLE ? FE_INVALID : 0) |
(status & DIVBYZERO_ENABLE ? FE_DIVBYZERO : 0) |
(status & OVERFLOW_ENABLE ? FE_OVERFLOW : 0) |
(status & UNDERFLOW_ENABLE ? FE_UNDERFLOW : 0) |
(status & INEXACT_ENABLE ? FE_INEXACT : 0);
return ((status & INVALID_ENABLE) ? FE_INVALID : 0) |
((status & DIVBYZERO_ENABLE) ? FE_DIVBYZERO : 0) |
((status & OVERFLOW_ENABLE) ? FE_OVERFLOW : 0) |
((status & UNDERFLOW_ENABLE) ? FE_UNDERFLOW : 0) |
((status & INEXACT_ENABLE) ? FE_INEXACT : 0);
}

LIBC_INLINE static uint32_t exception_macro_to_enable_bits(int except) {
return (except & FE_INVALID ? INVALID_ENABLE : 0) |
(except & FE_DIVBYZERO ? DIVBYZERO_ENABLE : 0) |
(except & FE_OVERFLOW ? OVERFLOW_ENABLE : 0) |
(except & FE_UNDERFLOW ? UNDERFLOW_ENABLE : 0) |
(except & FE_INEXACT ? INEXACT_ENABLE : 0);
return ((except & FE_INVALID) ? INVALID_ENABLE : 0) |
((except & FE_DIVBYZERO) ? DIVBYZERO_ENABLE : 0) |
((except & FE_OVERFLOW) ? OVERFLOW_ENABLE : 0) |
((except & FE_UNDERFLOW) ? UNDERFLOW_ENABLE : 0) |
((except & FE_INEXACT) ? INEXACT_ENABLE : 0);
}

LIBC_INLINE static uint32_t exception_macro_to_status_bits(int except) {
return (except & FE_INVALID ? INVALID_STATUS : 0) |
(except & FE_DIVBYZERO ? DIVBYZERO_STATUS : 0) |
(except & FE_OVERFLOW ? OVERFLOW_STATUS : 0) |
(except & FE_UNDERFLOW ? UNDERFLOW_STATUS : 0) |
(except & FE_INEXACT ? INEXACT_STATUS : 0);
return ((except & FE_INVALID) ? INVALID_STATUS : 0) |
((except & FE_DIVBYZERO) ? DIVBYZERO_STATUS : 0) |
((except & FE_OVERFLOW) ? OVERFLOW_STATUS : 0) |
((except & FE_UNDERFLOW) ? UNDERFLOW_STATUS : 0) |
((except & FE_INEXACT) ? INEXACT_STATUS : 0);
}

LIBC_INLINE static uint32_t exception_status_bits_to_macro(int status) {
return (status & INVALID_STATUS ? FE_INVALID : 0) |
(status & DIVBYZERO_STATUS ? FE_DIVBYZERO : 0) |
(status & OVERFLOW_STATUS ? FE_OVERFLOW : 0) |
(status & UNDERFLOW_STATUS ? FE_UNDERFLOW : 0) |
(status & INEXACT_STATUS ? FE_INEXACT : 0);
return ((status & INVALID_STATUS) ? FE_INVALID : 0) |
((status & DIVBYZERO_STATUS) ? FE_DIVBYZERO : 0) |
((status & OVERFLOW_STATUS) ? FE_OVERFLOW : 0) |
((status & UNDERFLOW_STATUS) ? FE_UNDERFLOW : 0) |
((status & INEXACT_STATUS) ? FE_INEXACT : 0);
}
};

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20 changes: 10 additions & 10 deletions libc/src/__support/FPUtil/riscv/FEnvImpl.h
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Expand Up @@ -65,19 +65,19 @@ struct FEnv {
}

LIBC_INLINE static int exception_bits_to_macro(uint32_t status) {
return (status & INVALID ? FE_INVALID : 0) |
(status & DIVBYZERO ? FE_DIVBYZERO : 0) |
(status & OVERFLOW ? FE_OVERFLOW : 0) |
(status & UNDERFLOW ? FE_UNDERFLOW : 0) |
(status & INEXACT ? FE_INEXACT : 0);
return ((status & INVALID) ? FE_INVALID : 0) |
((status & DIVBYZERO) ? FE_DIVBYZERO : 0) |
((status & OVERFLOW) ? FE_OVERFLOW : 0) |
((status & UNDERFLOW) ? FE_UNDERFLOW : 0) |
((status & INEXACT) ? FE_INEXACT : 0);
}

LIBC_INLINE static uint32_t exception_macro_to_bits(int except) {
return (except & FE_INVALID ? INVALID : 0) |
(except & FE_DIVBYZERO ? DIVBYZERO : 0) |
(except & FE_OVERFLOW ? OVERFLOW : 0) |
(except & FE_UNDERFLOW ? UNDERFLOW : 0) |
(except & FE_INEXACT ? INEXACT : 0);
return ((except & FE_INVALID) ? INVALID : 0) |
((except & FE_DIVBYZERO) ? DIVBYZERO : 0) |
((except & FE_OVERFLOW) ? OVERFLOW : 0) |
((except & FE_UNDERFLOW) ? UNDERFLOW : 0) |
((except & FE_INEXACT) ? INEXACT : 0);
}
};

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24 changes: 12 additions & 12 deletions libc/src/__support/FPUtil/x86_64/FEnvImpl.h
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Expand Up @@ -72,25 +72,25 @@ static constexpr uint16_t MXCSR_EXCEPTION_CONTOL_BIT_POISTION = 7;
LIBC_INLINE uint16_t get_status_value_for_except(int excepts) {
// We will make use of the fact that exception control bits are single
// bit flags in the control registers.
return (excepts & FE_INVALID ? ExceptionFlags::INVALID_F : 0) |
return ((excepts & FE_INVALID) ? ExceptionFlags::INVALID_F : 0) |
#ifdef __FE_DENORM
(excepts & __FE_DENORM ? ExceptionFlags::DENORMAL_F : 0) |
((excepts & __FE_DENORM) ? ExceptionFlags::DENORMAL_F : 0) |
#endif // __FE_DENORM
(excepts & FE_DIVBYZERO ? ExceptionFlags::DIV_BY_ZERO_F : 0) |
(excepts & FE_OVERFLOW ? ExceptionFlags::OVERFLOW_F : 0) |
(excepts & FE_UNDERFLOW ? ExceptionFlags::UNDERFLOW_F : 0) |
(excepts & FE_INEXACT ? ExceptionFlags::INEXACT_F : 0);
((excepts & FE_DIVBYZERO) ? ExceptionFlags::DIV_BY_ZERO_F : 0) |
((excepts & FE_OVERFLOW) ? ExceptionFlags::OVERFLOW_F : 0) |
((excepts & FE_UNDERFLOW) ? ExceptionFlags::UNDERFLOW_F : 0) |
((excepts & FE_INEXACT) ? ExceptionFlags::INEXACT_F : 0);
}

LIBC_INLINE int exception_status_to_macro(uint16_t status) {
return (status & ExceptionFlags::INVALID_F ? FE_INVALID : 0) |
return ((status & ExceptionFlags::INVALID_F) ? FE_INVALID : 0) |
#ifdef __FE_DENORM
(status & ExceptionFlags::DENORMAL_F ? __FE_DENORM : 0) |
((status & ExceptionFlags::DENORMAL_F) ? __FE_DENORM : 0) |
#endif // __FE_DENORM
(status & ExceptionFlags::DIV_BY_ZERO_F ? FE_DIVBYZERO : 0) |
(status & ExceptionFlags::OVERFLOW_F ? FE_OVERFLOW : 0) |
(status & ExceptionFlags::UNDERFLOW_F ? FE_UNDERFLOW : 0) |
(status & ExceptionFlags::INEXACT_F ? FE_INEXACT : 0);
((status & ExceptionFlags::DIV_BY_ZERO_F) ? FE_DIVBYZERO : 0) |
((status & ExceptionFlags::OVERFLOW_F) ? FE_OVERFLOW : 0) |
((status & ExceptionFlags::UNDERFLOW_F) ? FE_UNDERFLOW : 0) |
((status & ExceptionFlags::INEXACT_F) ? FE_INEXACT : 0);
}

struct X87StateDescriptor {
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2 changes: 1 addition & 1 deletion libclc/generic/lib/math/log_base.h
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Expand Up @@ -289,7 +289,7 @@ log(double x)
double ret = is_near ? ret_near : ret_far;

ret = isinf(x) ? as_double(PINFBITPATT_DP64) : ret;
ret = isnan(x) | (x < 0.0) ? as_double(QNANBITPATT_DP64) : ret;
ret = (isnan(x) | (x < 0.0)) ? as_double(QNANBITPATT_DP64) : ret;
ret = x == 0.0 ? as_double(NINFBITPATT_DP64) : ret;
return ret;
}
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4 changes: 1 addition & 3 deletions libcxxabi/src/cxa_personality.cpp
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Expand Up @@ -717,9 +717,7 @@ static void scan_eh_tab(scan_results &results, _Unwind_Action actions,
if (actionEntry == 0)
{
// Found a cleanup
results.reason = actions & _UA_SEARCH_PHASE
? _URC_CONTINUE_UNWIND
: _URC_HANDLER_FOUND;
results.reason = (actions & _UA_SEARCH_PHASE) ? _URC_CONTINUE_UNWIND : _URC_HANDLER_FOUND;
return;
}
// Convert 1-based byte offset into
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2 changes: 1 addition & 1 deletion lld/ELF/LinkerScript.cpp
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Expand Up @@ -801,7 +801,7 @@ static OutputDesc *addInputSec(StringMap<TinyPtrVector<OutputSection *>> &map,
auto *firstIsec = cast<InputSectionBase>(
cast<InputSectionDescription>(sec->commands[0])->sectionBases[0]);
OutputSection *firstIsecOut =
firstIsec->flags & SHF_LINK_ORDER
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Why is random change made to lld/ELF?

[-+*%] \w+ \?' is extensively used and I don't see we add )

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Hi @MaskRay ,

the PR modifies all the files with non-trivial ternary operators given by Cppcheck (issue).
You can find the Cppcheck report inside the comments thread of the issue.

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A CppCheck issue may or may not be useful for the project. Projects have different code styles. Applying a random static analyzer report may not be useful.

(firstIsec->flags & SHF_LINK_ORDER)
? firstIsec->getLinkOrderDep()->getOutputSection()
: nullptr;
if (firstIsecOut != isec->getLinkOrderDep()->getOutputSection())
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2 changes: 1 addition & 1 deletion lldb/tools/debugserver/source/MacOSX/MachException.cpp
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Expand Up @@ -247,7 +247,7 @@ kern_return_t MachException::Message::Receive(mach_port_t port,
DNBError err;
const bool log_exceptions = DNBLogCheckLogBit(LOG_EXCEPTIONS);
mach_msg_timeout_t mach_msg_timeout =
options & MACH_RCV_TIMEOUT ? timeout : 0;
(options & MACH_RCV_TIMEOUT) ? timeout : 0;
if (log_exceptions && ((options & MACH_RCV_TIMEOUT) == 0)) {
// Dump this log message if we have no timeout in case it never returns
DNBLogThreaded("::mach_msg ( msg->{bits = %#x, size = %u remote_port = "
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Expand Up @@ -3910,8 +3910,8 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
int RSrcOpName = Desc.TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc
: AMDGPU::OpName::rsrc;
int RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc
: AMDGPU::OpName::rsrc;
int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RSrcOpName);
int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16);
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Expand Up @@ -921,8 +921,8 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
AMDGPU::OpName::vdata);
int VAddr0Idx =
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc
: AMDGPU::OpName::rsrc;
int RsrcOpName = (TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc
: AMDGPU::OpName::rsrc;
int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName);
int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
AMDGPU::OpName::dmask);
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4 changes: 2 additions & 2 deletions llvm/lib/Target/AVR/AVRAsmPrinter.cpp
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Expand Up @@ -134,8 +134,8 @@ bool AVRAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
Reg = MI->getOperand(OpNum + RegIdx).getReg();

if (BytesPerReg == 2) {
Reg = TRI.getSubReg(Reg,
ByteNumber % BytesPerReg ? AVR::sub_hi : AVR::sub_lo);
Reg = TRI.getSubReg(Reg, (ByteNumber % BytesPerReg) ? AVR::sub_hi
: AVR::sub_lo);
}

O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI);
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4 changes: 2 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
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Expand Up @@ -2101,8 +2101,8 @@ prepareCompareSwapOperands(MachineBasicBlock::iterator const MBBI) const {

unsigned SystemZ::reverseCCMask(unsigned CCMask) {
return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
(CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
(CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
((CCMask & SystemZ::CCMASK_CMP_GT) ? SystemZ::CCMASK_CMP_LT : 0) |
((CCMask & SystemZ::CCMASK_CMP_LT) ? SystemZ::CCMASK_CMP_GT : 0) |
(CCMask & SystemZ::CCMASK_CMP_UO));
}

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2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
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Expand Up @@ -3802,7 +3802,7 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
// VFMULCPHZrr Dest, Src1, Src2
// VFMULCPHZrrk Dest, Dest, Mask, Src1, Src2
// VFMULCPHZrrkz Dest, Mask, Src1, Src2
for (unsigned i = TSFlags & X86II::EVEX_K ? 2 : 1;
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I know it's subjective, but the new code with two levels of parens decreases readability.

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The second level seems like a bug, it's not consistent with how type identifier = expr ? expr : expr; is handled in a block.

for (unsigned i = ((TSFlags & X86II::EVEX_K) ? 2 : 1);
i < Inst.getNumOperands(); i++)
if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg())
return Warning(Ops[0]->getStartLoc(), "Destination register should be "
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2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
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Expand Up @@ -980,7 +980,7 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
break;
case X86II::VEX:
// VEX can be 2 byte or 3 byte, not determined yet if not explicit
Prefix.setLowerBound(MI.getFlags() & X86::IP_USE_VEX3 ? VEX3 : VEX2);
Prefix.setLowerBound((MI.getFlags() & X86::IP_USE_VEX3) ? VEX3 : VEX2);
break;
case X86II::EVEX:
Prefix.setLowerBound(EVEX);
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4 changes: 2 additions & 2 deletions mlir/lib/Dialect/Tosa/Transforms/TosaDecomposeTransposeConv.cpp
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Expand Up @@ -182,9 +182,9 @@ class TransposeConvStridedConverter
// Pad the weight so that it is modulo of the striding.
llvm::SmallVector<int32_t, 8> weightPadding = {0, 0, 0, 0, 0, 0, 0, 0};
weightPadding[3] =
weightHeight % stride[0] ? stride[0] - weightHeight % stride[0] : 0;
(weightHeight % stride[0]) ? (stride[0] - weightHeight % stride[0]) : 0;
weightPadding[5] =
weightWidth % stride[1] ? stride[1] - weightWidth % stride[1] : 0;
(weightWidth % stride[1]) ? (stride[1] - weightWidth % stride[1]) : 0;
DenseElementsAttr weightPaddingAttr = DenseIntElementsAttr::get(
RankedTensorType::get({4, 2}, rewriter.getI32Type()), weightPadding);
Value weightPaddingVal = createOpAndInfer<tosa::ConstOp>(
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