Skip to content

[RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. #90428

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Apr 29, 2024
Merged

[RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 combines. #90428

Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
71af4bc
[RISCV] Break the (czero_eqz x, (setne x, 0)) -> x combine into 2 com…
topperc Apr 29, 2024
c30f921
fixup! Fix mistakes
topperc Apr 29, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
50 changes: 29 additions & 21 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16165,28 +16165,36 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return performSELECTCombine(N, DAG, Subtarget);
case RISCVISD::CZERO_EQZ:
case RISCVISD::CZERO_NEZ: {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
// czero_eq X, (xor Y, 1) -> czero_ne X, Y if Y is 0 or 1.
// czero_ne X, (xor Y, 1) -> czero_eq X, Y if Y is 0 or 1.
if (RHS.getOpcode() == ISD::XOR && isOneConstant(RHS.getOperand(1))) {
SDValue Cond = RHS.getOperand(0);
APInt Mask = APInt::getBitsSetFrom(Cond.getValueSizeInBits(), 1);
if (DAG.MaskedValueIsZero(Cond, Mask)) {
unsigned NewOpc = N->getOpcode() == RISCVISD::CZERO_EQZ
? RISCVISD::CZERO_NEZ
: RISCVISD::CZERO_EQZ;
return DAG.getNode(NewOpc, SDLoc(N), N->getValueType(0), LHS, Cond);
}
SDValue Val = N->getOperand(0);
SDValue Cond = N->getOperand(1);

unsigned Opc = N->getOpcode();

// czero_eqz x, x -> x
if (Opc == RISCVISD::CZERO_EQZ && Val == Cond)
return Val;

unsigned InvOpc =
Opc == RISCVISD::CZERO_EQZ ? RISCVISD::CZERO_NEZ : RISCVISD::CZERO_EQZ;

// czero_eqz X, (xor Y, 1) -> czero_nez X, Y if Y is 0 or 1.
// czero_nez X, (xor Y, 1) -> czero_eqz X, Y if Y is 0 or 1.
if (Cond.getOpcode() == ISD::XOR && isOneConstant(Cond.getOperand(1))) {
SDValue NewCond = Cond.getOperand(0);
APInt Mask = APInt::getBitsSetFrom(NewCond.getValueSizeInBits(), 1);
if (DAG.MaskedValueIsZero(NewCond, Mask))
return DAG.getNode(InvOpc, SDLoc(N), N->getValueType(0), Val, NewCond);
}
// czero_eqz x, (setcc y, 0, ne) -> czero_eqz x, y
// czero_nez x, (setcc y, 0, ne) -> czero_nez x, y
// czero_eqz x, (setcc y, 0, eq) -> czero_nez x, y
// czero_nez x, (setcc y, 0, eq) -> czero_eqz x, y
if (Cond.getOpcode() == ISD::SETCC && isNullConstant(Cond.getOperand(1))) {
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think the following logic can be removed now.

llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td

Lines 42 to 49 in 3785d74

def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
(CZERO_EQZ GPR:$rs1, GPR:$rc)>;
def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
(CZERO_NEZ GPR:$rs1, GPR:$rc)>;
def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
(CZERO_NEZ GPR:$rs1, GPR:$rc)>;
def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
(CZERO_EQZ GPR:$rs1, GPR:$rc)>;

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Those can't remove removed. They handle cases other than RHS being 0.

ISD::CondCode CCVal = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
if (ISD::isIntEqualitySetCC(CCVal))
return DAG.getNode(CCVal == ISD::SETNE ? Opc : InvOpc, SDLoc(N),
N->getValueType(0), Val, Cond.getOperand(0));
}
// czero_eqz x, (setcc x, 0, ne) -> x
// czero_nez x, (setcc x, 0, eq) -> x
if (RHS.getOpcode() == ISD::SETCC && isNullConstant(RHS.getOperand(1)) &&
cast<CondCodeSDNode>(RHS.getOperand(2))->get() ==
(N->getOpcode() == RISCVISD::CZERO_EQZ ? ISD::CondCode::SETNE
: ISD::CondCode::SETEQ) &&
LHS == RHS.getOperand(0))
return LHS;
return SDValue();
}
case RISCVISD::SELECT_CC: {
Expand Down