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[RISCV] Run DeadMachineInstructionElim after regalloc #90598

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[RISCV] Run DeadMachineInstructionElim after regalloc #90598

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21 changes: 1 addition & 20 deletions llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1402,20 +1402,9 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
if (RISCVII::hasVLOp(TSFlags)) {
MachineOperand &VLOp = MI.getOperand(getVLOpNum(MI));
if (VLOp.isReg()) {
Register Reg = VLOp.getReg();
MachineInstr *VLOpDef = MRI->getVRegDef(Reg);

// Erase the AVL operand from the instruction.
VLOp.setReg(RISCV::NoRegister);
VLOp.setIsKill(false);

// If the AVL was an immediate > 31, then it would have been emitted
// as an ADDI. However, the ADDI might not have been used in the
// vsetvli, or a vsetvli might not have been emitted, so it may be
// dead now.
if (VLOpDef && TII->isAddImmediate(*VLOpDef, Reg) &&
MRI->use_nodbg_empty(Reg))
VLOpDef->eraseFromParent();
}
MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false,
/*isImp*/ true));
Expand Down Expand Up @@ -1670,17 +1659,9 @@ bool RISCVCoalesceVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) {
if (NextMI->getOperand(1).isReg())
NextMI->getOperand(1).setReg(RISCV::NoRegister);

if (OldVLReg && OldVLReg.isVirtual()) {
if (OldVLReg && OldVLReg.isVirtual())
// NextMI no longer uses OldVLReg so shrink its LiveInterval.
LIS->shrinkToUses(&LIS->getInterval(OldVLReg));

MachineInstr *VLOpDef = MRI->getUniqueVRegDef(OldVLReg);
if (VLOpDef && TII->isAddImmediate(*VLOpDef, OldVLReg) &&
MRI->use_nodbg_empty(OldVLReg)) {
VLOpDef->eraseFromParent();
LIS->removeInterval(OldVLReg);
}
}
MI.setDesc(NextMI->getDesc());
}
MI.getOperand(2).setImm(NextMI->getOperand(2).getImm());
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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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Expand Up @@ -553,6 +553,8 @@ void RISCVPassConfig::addPostRegAlloc() {
if (TM->getOptLevel() != CodeGenOptLevel::None &&
EnableRedundantCopyElimination)
addPass(createRISCVRedundantCopyEliminationPass());
// RISCVInsertVSETVLI may leave some defs of AVLs dead, so remove them.
addPass(&DeadMachineInstructionElimID);
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Please update O3-pipeline.ll

}

yaml::MachineFunctionInfo *
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13 changes: 6 additions & 7 deletions llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
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Expand Up @@ -29,13 +29,12 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O0-NEXT: lui a0, %hi(.L.str)
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
; SPILL-O0-NEXT: call puts
; SPILL-O0-NEXT: addi a1, sp, 16
; SPILL-O0-NEXT: vl1r.v v10, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 16
; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: # kill: def $x11 killed $x10
; SPILL-O0-NEXT: addi a0, sp, 16
; SPILL-O0-NEXT: vl1r.v v10, (a0) # Unknown-size Folded Reload
; SPILL-O0-NEXT: csrr a0, vlenb
; SPILL-O0-NEXT: add a0, sp, a0
; SPILL-O0-NEXT: addi a0, a0, 16
; SPILL-O0-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
; SPILL-O0-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; SPILL-O0-NEXT: # implicit-def: $v8
Expand Down
11 changes: 0 additions & 11 deletions llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
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Expand Up @@ -14,9 +14,7 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i32 %vl) nounwind {
; SPILL-O0-NEXT: slli a2, a2, 1
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: # implicit-def: $v9
; SPILL-O0-NEXT: # implicit-def: $v10
; SPILL-O0-NEXT: # implicit-def: $v9
; SPILL-O0-NEXT: # kill: def $v8 killed $v8 def $v8_v9
; SPILL-O0-NEXT: vmv1r.v v9, v10
; SPILL-O0-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
Expand Down Expand Up @@ -96,9 +94,7 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i32 %vl) nounwind {
; SPILL-O0-NEXT: slli a2, a2, 1
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: # implicit-def: $v9
; SPILL-O0-NEXT: # implicit-def: $v10
; SPILL-O0-NEXT: # implicit-def: $v9
; SPILL-O0-NEXT: # kill: def $v8 killed $v8 def $v8_v9
; SPILL-O0-NEXT: vmv1r.v v9, v10
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m1, ta, ma
Expand Down Expand Up @@ -178,9 +174,7 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i32 %vl) nounwind {
; SPILL-O0-NEXT: slli a2, a2, 1
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: # implicit-def: $v8m2
; SPILL-O0-NEXT: # implicit-def: $v10m2
; SPILL-O0-NEXT: # implicit-def: $v12m2
; SPILL-O0-NEXT: # implicit-def: $v10m2
; SPILL-O0-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
; SPILL-O0-NEXT: vmv2r.v v10, v12
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, ma
Expand Down Expand Up @@ -263,9 +257,7 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i32 %vl) nounwind {
; SPILL-O0-NEXT: slli a2, a2, 2
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: # implicit-def: $v8m4
; SPILL-O0-NEXT: # implicit-def: $v12m4
; SPILL-O0-NEXT: # implicit-def: $v16m4
; SPILL-O0-NEXT: # implicit-def: $v12m4
; SPILL-O0-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; SPILL-O0-NEXT: vmv4r.v v12, v16
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m4, ta, ma
Expand Down Expand Up @@ -348,11 +340,8 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i32 %vl) nounwind {
; SPILL-O0-NEXT: slli a2, a2, 1
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: # implicit-def: $v8m2
; SPILL-O0-NEXT: # implicit-def: $v10m2
; SPILL-O0-NEXT: # implicit-def: $v16m2
; SPILL-O0-NEXT: # implicit-def: $v10m2
; SPILL-O0-NEXT: # implicit-def: $v14m2
; SPILL-O0-NEXT: # implicit-def: $v10m2
; SPILL-O0-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
; SPILL-O0-NEXT: vmv2r.v v10, v16
; SPILL-O0-NEXT: vmv2r.v v12, v14
Expand Down
13 changes: 6 additions & 7 deletions llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
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Expand Up @@ -32,13 +32,12 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O0-NEXT: lui a0, %hi(.L.str)
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
; SPILL-O0-NEXT: call puts
; SPILL-O0-NEXT: addi a1, sp, 32
; SPILL-O0-NEXT: vl1r.v v10, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 32
; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: # kill: def $x11 killed $x10
; SPILL-O0-NEXT: addi a0, sp, 32
; SPILL-O0-NEXT: vl1r.v v10, (a0) # Unknown-size Folded Reload
; SPILL-O0-NEXT: csrr a0, vlenb
; SPILL-O0-NEXT: add a0, sp, a0
; SPILL-O0-NEXT: addi a0, a0, 32
; SPILL-O0-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
; SPILL-O0-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; SPILL-O0-NEXT: # implicit-def: $v8
Expand Down
11 changes: 0 additions & 11 deletions llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
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Expand Up @@ -14,9 +14,7 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i64 %vl) nounwind {
; SPILL-O0-NEXT: slli a2, a2, 1
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: # implicit-def: $v9
; SPILL-O0-NEXT: # implicit-def: $v10
; SPILL-O0-NEXT: # implicit-def: $v9
; SPILL-O0-NEXT: # kill: def $v8 killed $v8 def $v8_v9
; SPILL-O0-NEXT: vmv1r.v v9, v10
; SPILL-O0-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
Expand Down Expand Up @@ -96,9 +94,7 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i64 %vl) nounwind {
; SPILL-O0-NEXT: slli a2, a2, 1
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: # implicit-def: $v9
; SPILL-O0-NEXT: # implicit-def: $v10
; SPILL-O0-NEXT: # implicit-def: $v9
; SPILL-O0-NEXT: # kill: def $v8 killed $v8 def $v8_v9
; SPILL-O0-NEXT: vmv1r.v v9, v10
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m1, ta, ma
Expand Down Expand Up @@ -178,9 +174,7 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i64 %vl) nounwind {
; SPILL-O0-NEXT: slli a2, a2, 1
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: # implicit-def: $v8m2
; SPILL-O0-NEXT: # implicit-def: $v10m2
; SPILL-O0-NEXT: # implicit-def: $v12m2
; SPILL-O0-NEXT: # implicit-def: $v10m2
; SPILL-O0-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2
; SPILL-O0-NEXT: vmv2r.v v10, v12
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, ma
Expand Down Expand Up @@ -263,9 +257,7 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i64 %vl) nounwind {
; SPILL-O0-NEXT: slli a2, a2, 2
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: # implicit-def: $v8m4
; SPILL-O0-NEXT: # implicit-def: $v12m4
; SPILL-O0-NEXT: # implicit-def: $v16m4
; SPILL-O0-NEXT: # implicit-def: $v12m4
; SPILL-O0-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; SPILL-O0-NEXT: vmv4r.v v12, v16
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m4, ta, ma
Expand Down Expand Up @@ -348,11 +340,8 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i64 %vl) nounwind {
; SPILL-O0-NEXT: slli a2, a2, 1
; SPILL-O0-NEXT: sub sp, sp, a2
; SPILL-O0-NEXT: # implicit-def: $v8m2
; SPILL-O0-NEXT: # implicit-def: $v10m2
; SPILL-O0-NEXT: # implicit-def: $v16m2
; SPILL-O0-NEXT: # implicit-def: $v10m2
; SPILL-O0-NEXT: # implicit-def: $v14m2
; SPILL-O0-NEXT: # implicit-def: $v10m2
; SPILL-O0-NEXT: # kill: def $v8m2 killed $v8m2 def $v8m2_v10m2_v12m2
; SPILL-O0-NEXT: vmv2r.v v10, v16
; SPILL-O0-NEXT: vmv2r.v v12, v14
Expand Down
2 changes: 0 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
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Expand Up @@ -91,13 +91,11 @@ define <vscale x 1 x double> @test3(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, ma
; CHECK-NEXT: vfadd.vv v9, v8, v9
; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: # implicit-def: $x10
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: # %if.else
; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, ma
; CHECK-NEXT: vfsub.vv v9, v8, v9
; CHECK-NEXT: vfmul.vv v8, v9, v8
; CHECK-NEXT: # implicit-def: $x10
; CHECK-NEXT: ret
entry:
%tobool = icmp eq i8 %cond, 0
Expand Down