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[SelectionDAG][X86] Add a NoWrap flag to SelectionDAG::isAddLike. NFC #90681

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Merged
merged 1 commit into from
Apr 30, 2024
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[SelectionDAG][X86] Add a NoWrap flag to SelectionDAG::isAddLike. NFC #90681

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5 changes: 3 additions & 2 deletions llvm/include/llvm/CodeGen/SelectionDAG.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2083,8 +2083,9 @@ class SelectionDAG {
/// Return true if the specified operand is an ISD::OR or ISD::XOR node
/// that can be treated as an ISD::ADD node.
/// or(x,y) == add(x,y) iff haveNoCommonBitsSet(x,y)
/// xor(x,y) == add(x,y) iff isMinSignedConstant(y)
bool isADDLike(SDValue Op) const;
/// xor(x,y) == add(x,y) iff isMinSignedConstant(y) && !NoWrap
/// If \p NoWrap is true, this will not match ISD::XOR.
bool isADDLike(SDValue Op, bool NoWrap = false) const;

/// Return true if the specified operand is an ISD::ADD with a ConstantSDNode
/// on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that
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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -5231,13 +5231,13 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
return true;
}

bool SelectionDAG::isADDLike(SDValue Op) const {
bool SelectionDAG::isADDLike(SDValue Op, bool NoWrap) const {
unsigned Opcode = Op.getOpcode();
if (Opcode == ISD::OR)
return Op->getFlags().hasDisjoint() ||
haveNoCommonBitsSet(Op.getOperand(0), Op.getOperand(1));
if (Opcode == ISD::XOR)
return isMinSignedConstant(Op.getOperand(1));
return !NoWrap && isMinSignedConstant(Op.getOperand(1));
return false;
}

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2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
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Expand Up @@ -2353,7 +2353,7 @@ SDValue X86DAGToDAGISel::matchIndexRecursively(SDValue N,
SDValue Src = N.getOperand(0);
unsigned SrcOpc = Src.getOpcode();
if (((SrcOpc == ISD::ADD && Src->getFlags().hasNoUnsignedWrap()) ||
CurDAG->isADDLike(Src)) &&
CurDAG->isADDLike(Src, /*NoWrap=*/true)) &&
Src.hasOneUse()) {
if (CurDAG->isBaseWithConstantOffset(Src)) {
SDValue AddSrc = Src.getOperand(0);
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3 changes: 2 additions & 1 deletion llvm/test/CodeGen/X86/pr90668.ll
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Expand Up @@ -4,8 +4,9 @@
define i64 @off(i8 signext %a) {
; CHECK-LABEL: off:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addb $-128, %dil
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: leal 1024(,%rax,8), %eax
; CHECK-NEXT: shll $3, %eax
; CHECK-NEXT: retq
entry:
%add = xor i8 %a, -128
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