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[TII][RISCV] Add renamable bit to copyPhysReg #91179

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Merged
merged 3 commits into from
Aug 27, 2024
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[TII][RISCV] Add renamable bit to copyPhysReg #91179

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28da84c
[TII][NFC] Add renamable bit to copyPhysReg
BeMg May 6, 2024
eb1120c
document the new arguments
BeMg May 7, 2024
af4c3e7
Update RISCVInstrInfo::copyPhysReg with renamable ADDI
BeMg Aug 26, 2024
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10 changes: 8 additions & 2 deletions llvm/include/llvm/CodeGen/TargetInstrInfo.h
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Expand Up @@ -1018,10 +1018,16 @@ class TargetInstrInfo : public MCInstrInfo {
/// The source and destination registers may overlap, which may require a
/// careful implementation when multiple copy instructions are required for
/// large registers. See for example the ARM target.
///
/// If RenamableDest is true, the copy instruction's destination operand is
/// marked renamable.
/// If RenamableSrc is true, the copy instruction's source operand is
/// marked renamable.
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, const DebugLoc &DL,
MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const {
MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
bool RenamableDest = false,
bool RenamableSrc = false) const {
Comment on lines +1028 to +1030
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Should we just start passing through a SrcFlags/DestFlags instead of unpacking them into kill/renamable?

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Or pass in actual MachineOperands for src and dest? Or an actual COPY instruction?

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I think passing in MachineOperands would be wrong, you should be able to use this without an existing COPY instruction

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I think passing in MachineOperands would be wrong, you should be able to use this without an existing COPY instruction

Agree!

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you should be able to use this without an existing COPY instruction

In that case you can create standalone MachineOperands to pass the information into copyPhysReg. I'm just suggesting this as a bit of a hack, because MachineOperand currently does not store its flags in such a way that they can easily be copied in/out of operands and passed around in APIs.

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@arsenm arsenm May 8, 2024 •
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Having to construct temporary operands would be worse than just having a bool flag for every bit. They're not exactly free to allocate

llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
}

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4 changes: 3 additions & 1 deletion llvm/lib/CodeGen/TargetInstrInfo.cpp
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Expand Up @@ -823,7 +823,9 @@ void TargetInstrInfo::lowerCopy(MachineInstr *MI,
}

copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(), DstMO.getReg(),
SrcMO.getReg(), SrcMO.isKill());
SrcMO.getReg(), SrcMO.isKill(),
DstMO.getReg().isPhysical() ? DstMO.isRenamable() : false,
SrcMO.getReg().isPhysical() ? SrcMO.isRenamable() : false);

if (MI->getNumOperands() > 2)
transferImplicitOperands(MI, TRI);
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4 changes: 3 additions & 1 deletion llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Expand Up @@ -4851,7 +4851,9 @@ void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest,
bool RenamableSrc) const {
if (AArch64::GPR32spRegClass.contains(DestReg) &&
(AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
const TargetRegisterInfo *TRI = &getRegisterInfo();
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AArch64/AArch64InstrInfo.h
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Expand Up @@ -344,7 +344,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
llvm::ArrayRef<unsigned> Indices) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
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Expand Up @@ -40,7 +40,8 @@ bool R600InstrInfo::isVector(const MachineInstr &MI) const {
void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
unsigned VectorComponents = 0;
if ((R600::R600_Reg128RegClass.contains(DestReg) ||
R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/R600InstrInfo.h
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Expand Up @@ -73,7 +73,8 @@ class R600InstrInfo final : public R600GenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) const override;

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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Expand Up @@ -794,7 +794,8 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
unsigned Size = RI.getRegSizeInBits(*RC);
const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/SIInstrInfo.h
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Expand Up @@ -255,7 +255,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

void materializeImmediate(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, const DebugLoc &DL,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/ARC/ARCInstrInfo.cpp
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Expand Up @@ -281,7 +281,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
assert(ARC::GPR32RegClass.contains(SrcReg) &&
"Only GPR32 src copy supported.");
assert(ARC::GPR32RegClass.contains(DestReg) &&
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3 changes: 2 additions & 1 deletion llvm/lib/Target/ARC/ARCInstrInfo.h
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Expand Up @@ -65,7 +65,8 @@ class ARCInstrInfo : public ARCGenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register SrcReg,
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4 changes: 3 additions & 1 deletion llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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Expand Up @@ -892,7 +892,9 @@ void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,
void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest,
bool RenamableSrc) const {
bool GPRDest = ARM::GPRRegClass.contains(DestReg);
bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);

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3 changes: 2 additions & 1 deletion llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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Expand Up @@ -209,7 +209,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
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Expand Up @@ -42,7 +42,8 @@ unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
// Need to check the arch.
MachineFunction &MF = *MBB.getParent();
const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
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3 changes: 2 additions & 1 deletion llvm/lib/Target/ARM/Thumb1InstrInfo.h
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Expand Up @@ -39,7 +39,8 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
bool isKill, int FrameIndex,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
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Expand Up @@ -151,7 +151,8 @@ Thumb2InstrInfo::optimizeSelect(MachineInstr &MI,
void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
// Handle SPR, DPR, and QPR copies.
if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
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3 changes: 2 additions & 1 deletion llvm/lib/Target/ARM/Thumb2InstrInfo.h
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Expand Up @@ -39,7 +39,8 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AVR/AVRInstrInfo.cpp
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Expand Up @@ -42,7 +42,8 @@ AVRInstrInfo::AVRInstrInfo(AVRSubtarget &STI)
void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
unsigned Opc;

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3 changes: 2 additions & 1 deletion llvm/lib/Target/AVR/AVRInstrInfo.h
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Expand Up @@ -75,7 +75,8 @@ class AVRInstrInfo : public AVRGenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register SrcReg,
bool isKill, int FrameIndex,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/BPF/BPFInstrInfo.cpp
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Expand Up @@ -31,7 +31,8 @@ BPFInstrInfo::BPFInstrInfo()
void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
if (BPF::GPRRegClass.contains(DestReg, SrcReg))
BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
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3 changes: 2 additions & 1 deletion llvm/lib/Target/BPF/BPFInstrInfo.h
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Expand Up @@ -31,7 +31,8 @@ class BPFInstrInfo : public BPFGenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

bool expandPostRAPseudo(MachineInstr &MI) const override;

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3 changes: 2 additions & 1 deletion llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
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Expand Up @@ -478,7 +478,8 @@ void CSKYInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
if (CSKY::GPRRegClass.contains(SrcReg) &&
CSKY::CARRYRegClass.contains(DestReg)) {
if (STI.hasE2()) {
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3 changes: 2 additions & 1 deletion llvm/lib/Target/CSKY/CSKYInstrInfo.h
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Expand Up @@ -55,7 +55,8 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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4 changes: 3 additions & 1 deletion llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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Expand Up @@ -857,7 +857,9 @@ static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest,
bool RenamableSrc) const {
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
unsigned KillFlag = getKillRegState(KillSrc);

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3 changes: 2 additions & 1 deletion llvm/lib/Target/Hexagon/HexagonInstrInfo.h
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Expand Up @@ -174,7 +174,8 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
/// large registers. See for example the ARM target.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

/// Store the specified register of the given register class to the specified
/// stack frame index. The store instruction is to be added to the given
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4 changes: 2 additions & 2 deletions llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
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Expand Up @@ -35,8 +35,8 @@ void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator Position,
const DebugLoc &DL,
MCRegister DestinationRegister,
MCRegister SourceRegister,
bool KillSource) const {
MCRegister SourceRegister, bool KillSource,
bool RenamableDest, bool RenamableSrc) const {
if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
llvm_unreachable("Impossible reg-to-reg copy");
}
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4 changes: 3 additions & 1 deletion llvm/lib/Target/Lanai/LanaiInstrInfo.h
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Expand Up @@ -49,7 +49,9 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
const DebugLoc &DL, MCRegister DestinationRegister,
MCRegister SourceRegister, bool KillSource) const override;
MCRegister SourceRegister, bool KillSource,
bool RenamableDest = false,
bool RenamableSrc = false) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator Position,
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4 changes: 3 additions & 1 deletion llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp
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Expand Up @@ -39,7 +39,9 @@ MCInst LoongArchInstrInfo::getNop() const {
void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest,
bool RenamableSrc) const {
if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
.addReg(SrcReg, getKillRegState(KillSrc))
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3 changes: 2 additions & 1 deletion llvm/lib/Target/LoongArch/LoongArchInstrInfo.h
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Expand Up @@ -31,7 +31,8 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, Register SrcReg,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/M68k/M68kInstrInfo.cpp
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Expand Up @@ -663,7 +663,8 @@ bool M68kInstrInfo::isPCRelRegisterOperandLegal(
void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DstReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
unsigned Opc = 0;

// First deal with the normal symmetric copies.
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3 changes: 2 additions & 1 deletion llvm/lib/Target/M68k/M68kInstrInfo.h
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Expand Up @@ -271,7 +271,8 @@ class M68kInstrInfo : public M68kGenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
unsigned &Size, unsigned &Offset,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
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Expand Up @@ -90,7 +90,8 @@ void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
unsigned Opc;
if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
Opc = MSP430::MOV16rr;
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3 changes: 2 additions & 1 deletion llvm/lib/Target/MSP430/MSP430InstrInfo.h
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Expand Up @@ -37,7 +37,8 @@ class MSP430InstrInfo : public MSP430GenInstrInfo {

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
bool KillSrc) const override;
bool KillSrc, bool RenamableDest = false,
bool RenamableSrc = false) const override;

void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, Register SrcReg,
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3 changes: 2 additions & 1 deletion llvm/lib/Target/Mips/Mips16InstrInfo.cpp
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Expand Up @@ -69,7 +69,8 @@ Register Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
MCRegister SrcReg, bool KillSrc,
bool RenamableDest, bool RenamableSrc) const {
unsigned Opc = 0;

if (Mips::CPU16RegsRegClass.contains(DestReg) &&
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