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[Mips] Fix mfhi/mflo hazard miscompilation about div and mult #91449
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✅ With the latest revision this PR passed the C/C++ code formatter. |
Ping @wzssyqa |
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TII->insertNop(*(I->getParent()), std::next(I), I->getDebugLoc()) | ||
->bundleWithPred(); | ||
NumInsertedNops++; | ||
if (Predicate(*I) || |
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Why this condition is added here?
I guess you need some comment or description in commit msg.
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I would check again without this condition and add comment.
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I deleted this condition and the test result of ./build/bin/clang --target=mipsel-freestanding -mcpu=mips3 -fomit-frame-pointer -S 4.c -o 1.s
or with -O3
all are OK, I would update it. Maybe some reasons I added it now I forget. Thanks!
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Updated. I added a new function which makes it simpler.
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@wzssyqa Could you help review, thanks!
@@ -743,6 +743,12 @@ bool MipsDelaySlotFiller::searchRange(MachineBasicBlock &MBB, IterTy Begin, | |||
bool InMicroMipsMode = STI.inMicroMipsMode(); | |||
const MipsInstrInfo *TII = STI.getInstrInfo(); | |||
unsigned Opcode = (*Slot).getOpcode(); | |||
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if ((CurrI->getOpcode() == Mips::MFLO || |
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No MFHI here?
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I just address this title issue and forgot %
Modulo Operation. I would add it and related testcase.
Thanks for your review.
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Updated.
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Fix issue1: In mips1-4, require a minimum of 2 instructions between a mflo/mfhi and the next mul/dmult/div/ddiv/divu/ddivu instruction. Fix issue2: In mips1-4, should not put mflo into the delay slot for the return. Fix llvm#81291
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/190/builds/6306 Here is the relevant piece of the build log for the reference
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Fix issue1: In mips1-4, require a minimum of 2 instructions between a mflo/mfhi and the next mul/dmult/div/ddiv/divu/ddivu instruction.
Fix issue2: In mips1-4, should not put mflo into the delay slot for the return.
Fix #81291