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[RISCV] Add isel special case for (and (shl X, c2), c1) -> (slli_uw (srli x, c4-c2), c4). #91638

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Merged
merged 5 commits into from
May 9, 2024
Merged

[RISCV] Add isel special case for (and (shl X, c2), c1) -> (slli_uw (srli x, c4-c2), c4). #91638

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292763d
[RISCV] Add isel special case for (and (shl X, c2), c1) -> (slli_uw (…
topperc May 9, 2024
fc3c0b1
fixup! ensure Leading is greater than 0.
topperc May 9, 2024
0880607
fixup! Move code to a slighty different place with similar code.
topperc May 9, 2024
bc98e86
fixup! Add negative test that was previously broken.
topperc May 9, 2024
af400d0
fixup! Put comment back where I found it.
topperc May 9, 2024
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13 changes: 13 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1416,6 +1416,19 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, SLLI);
return;
}

// If we have 32 bits in the mask, we can use SLLI_UW instead of SLLI.
if (C2 < Trailing && Leading + Trailing == 32 && OneUseOrZExtW &&
Subtarget->hasStdExtZba()) {
SDNode *SRLI = CurDAG->getMachineNode(
RISCV::SRLI, DL, VT, X,
CurDAG->getTargetConstant(Trailing - C2, DL, VT));
SDNode *SLLI_UW = CurDAG->getMachineNode(
RISCV::SLLI_UW, DL, VT, SDValue(SRLI, 0),
CurDAG->getTargetConstant(Trailing, DL, VT));
ReplaceNode(Node, SLLI_UW);
return;
}
}
}

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40 changes: 36 additions & 4 deletions llvm/test/CodeGen/RISCV/rv64zba.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2866,8 +2866,7 @@ define ptr @gep_lshr_i32(ptr %0, i64 %1) {
;
; RV64ZBA-LABEL: gep_lshr_i32:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: slli a1, a1, 2
; RV64ZBA-NEXT: srli a1, a1, 4
; RV64ZBA-NEXT: srli a1, a1, 2
; RV64ZBA-NEXT: slli.uw a1, a1, 4
; RV64ZBA-NEXT: sh2add a1, a1, a1
; RV64ZBA-NEXT: add a0, a0, a1
Expand All @@ -2891,8 +2890,7 @@ define i64 @srli_slliw(i64 %1) {
;
; RV64ZBA-LABEL: srli_slliw:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: slli a0, a0, 2
; RV64ZBA-NEXT: srli a0, a0, 4
; RV64ZBA-NEXT: srli a0, a0, 2
; RV64ZBA-NEXT: slli.uw a0, a0, 4
; RV64ZBA-NEXT: ret
entry:
Expand All @@ -2902,6 +2900,40 @@ entry:
ret i64 %4
}

define i64 @srli_slliw_canonical(i64 %0) {
; RV64I-LABEL: srli_slliw_canonical:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 36
; RV64I-NEXT: addi a1, a1, -16
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: srli_slliw_canonical:
; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: srli a0, a0, 2
; RV64ZBA-NEXT: slli.uw a0, a0, 4
; RV64ZBA-NEXT: ret
entry:
%1 = shl i64 %0, 2
%2 = and i64 %1, 68719476720
ret i64 %2
}

; Make sure we don't accidentally use slli.uw with a shift of 32.
define i64 @srli_slliuw_negative_test(i64 %0) {
; CHECK-LABEL: srli_slliuw_negative_test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: srli a0, a0, 6
; CHECK-NEXT: slli a0, a0, 32
; CHECK-NEXT: ret
entry:
%1 = lshr i64 %0, 6
%2 = shl i64 %1, 32
ret i64 %2
}

define i64 @srli_slli_i16(i64 %1) {
; CHECK-LABEL: srli_slli_i16:
; CHECK: # %bb.0: # %entry
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