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[InstCombine] Fold vector.reduce.op(vector.reverse(X)) -> vector.reduce.op(X) #91743

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Merged
merged 6 commits into from
May 17, 2024
Merged

[InstCombine] Fold vector.reduce.op(vector.reverse(X)) -> vector.reduce.op(X) #91743

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f8cdf5c
[InstCombine] Fold vector.reduce.op(vector.reverse(X)) -> vector.redu…
david-arm May 10, 2024
4a238d6
Add simplifyReductionOfShuffle helper
david-arm May 13, 2024
bd1f234
Rename simplifyReductionOfShuffle -> simplifyReductionOperand
david-arm May 15, 2024
d553d1c
Address review comment
david-arm May 15, 2024
9eb2a1c
Make simplifyReductionOperand static
david-arm May 16, 2024
7923db5
Add comment to simplifyReductionOperand argument
david-arm May 17, 2024
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94 changes: 74 additions & 20 deletions llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1435,6 +1435,33 @@ static Instruction *foldBitOrderCrossLogicOp(Value *V,
return nullptr;
}

static Value *simplifyReductionOperand(Value *Arg, bool CanReorderLanes) {
if (!CanReorderLanes)
return nullptr;

Value *V;
if (match(Arg, m_VecReverse(m_Value(V))))
return V;

ArrayRef<int> Mask;
if (!isa<FixedVectorType>(Arg->getType()) ||
!match(Arg, m_Shuffle(m_Value(V), m_Undef(), m_Mask(Mask))) ||
!cast<ShuffleVectorInst>(Arg)->isSingleSource())
return nullptr;

int Sz = Mask.size();
SmallBitVector UsedIndices(Sz);
for (int Idx : Mask) {
if (Idx == PoisonMaskElem || UsedIndices.test(Idx))
return nullptr;
UsedIndices.set(Idx);
}

// Can remove shuffle iff just shuffled elements, no repeats, undefs, or
// other changes.
return UsedIndices.all() ? V : nullptr;
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Think the shuffle check could be simplified with getShuffleDemandedElts.

Then the check would just be:

if(DemandedLHS.isAllOnes() && DemandedRHS.isZero()) {
  return LHS;
}
if(DemandedRHS.isAllOnes() && DemandedLHS.isZero()) {
  return RHS;
}
return nullptr;

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Hmm, this is not a NFC change. I am not quite sure how to use getShuffleDemandedElts, but I'm pretty sure your example above now permits use of a RHS whereas previously it didn't (see !match(Arg, m_Shuffle(m_Value(V), m_Undef(), m_Mask(Mask)))). I would prefer to limit this to refactoring only as it's not relevant to this patch. I can keep the if(DemandedLHS.isAllOnes() ... check.

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I had a look at using getShuffleDemandedElts and the code didn't immediately look much better as I still need to keep most of the existing checks, i.e. check for isSingleSource and so on. For now, I'd prefer to leave the code as it is, but I'm happy to revisit this in a follow-on patch. Just out of curiosity, have you seen any examples where we pass through the 2nd operand of the shufflevector? i.e. reduce_or(shufflevector(<4 x i32> %a, <4 x i32> %b, <4 x i32> <7, 5, 6, 4>)). I'd expect this to be canonicalised to reduce_or(shufflevector(<4 x i32> %a, <4 x i32> undef, <4 x i32> <3, 1, 2, 0>))

}

/// CallInst simplification. This mostly only handles folding of intrinsic
/// instructions. For normal calls, it allows visitCallBase to do the heavy
/// lifting.
Expand Down Expand Up @@ -3223,6 +3250,13 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
// %res = cmp eq iReduxWidth %val, 11111
Value *Arg = II->getArgOperand(0);
Value *Vect;

if (Value *NewOp =
simplifyReductionOperand(Arg, /*CanReorderLanes=*/true)) {
replaceUse(II->getOperandUse(0), NewOp);
return II;
}

if (match(Arg, m_ZExtOrSExtOrSelf(m_Value(Vect)))) {
if (auto *FTy = dyn_cast<FixedVectorType>(Vect->getType()))
if (FTy->getElementType() == Builder.getInt1Ty()) {
Expand Down Expand Up @@ -3254,6 +3288,13 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
// Trunc(ctpop(bitcast <n x i1> to in)).
Value *Arg = II->getArgOperand(0);
Value *Vect;

if (Value *NewOp =
simplifyReductionOperand(Arg, /*CanReorderLanes=*/true)) {
replaceUse(II->getOperandUse(0), NewOp);
return II;
}

if (match(Arg, m_ZExtOrSExtOrSelf(m_Value(Vect)))) {
if (auto *FTy = dyn_cast<FixedVectorType>(Vect->getType()))
if (FTy->getElementType() == Builder.getInt1Ty()) {
Expand Down Expand Up @@ -3282,6 +3323,13 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
// ?ext(vector_reduce_add(<n x i1>))
Value *Arg = II->getArgOperand(0);
Value *Vect;

if (Value *NewOp =
simplifyReductionOperand(Arg, /*CanReorderLanes=*/true)) {
replaceUse(II->getOperandUse(0), NewOp);
return II;
}

if (match(Arg, m_ZExtOrSExtOrSelf(m_Value(Vect)))) {
if (auto *FTy = dyn_cast<FixedVectorType>(Vect->getType()))
if (FTy->getElementType() == Builder.getInt1Ty()) {
Expand All @@ -3305,6 +3353,13 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
// zext(vector_reduce_and(<n x i1>))
Value *Arg = II->getArgOperand(0);
Value *Vect;

if (Value *NewOp =
simplifyReductionOperand(Arg, /*CanReorderLanes=*/true)) {
replaceUse(II->getOperandUse(0), NewOp);
return II;
}

if (match(Arg, m_ZExtOrSExtOrSelf(m_Value(Vect)))) {
if (auto *FTy = dyn_cast<FixedVectorType>(Vect->getType()))
if (FTy->getElementType() == Builder.getInt1Ty()) {
Expand All @@ -3329,6 +3384,13 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
// ?ext(vector_reduce_{and,or}(<n x i1>))
Value *Arg = II->getArgOperand(0);
Value *Vect;

if (Value *NewOp =
simplifyReductionOperand(Arg, /*CanReorderLanes=*/true)) {
replaceUse(II->getOperandUse(0), NewOp);
return II;
}

if (match(Arg, m_ZExtOrSExtOrSelf(m_Value(Vect)))) {
if (auto *FTy = dyn_cast<FixedVectorType>(Vect->getType()))
if (FTy->getElementType() == Builder.getInt1Ty()) {
Expand Down Expand Up @@ -3364,6 +3426,13 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
// zext(vector_reduce_{and,or}(<n x i1>))
Value *Arg = II->getArgOperand(0);
Value *Vect;

if (Value *NewOp =
simplifyReductionOperand(Arg, /*CanReorderLanes=*/true)) {
replaceUse(II->getOperandUse(0), NewOp);
return II;
}

if (match(Arg, m_ZExtOrSExtOrSelf(m_Value(Vect)))) {
if (auto *FTy = dyn_cast<FixedVectorType>(Vect->getType()))
if (FTy->getElementType() == Builder.getInt1Ty()) {
Expand All @@ -3386,31 +3455,16 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
case Intrinsic::vector_reduce_fmin:
case Intrinsic::vector_reduce_fadd:
case Intrinsic::vector_reduce_fmul: {
bool CanBeReassociated = (IID != Intrinsic::vector_reduce_fadd &&
IID != Intrinsic::vector_reduce_fmul) ||
II->hasAllowReassoc();
bool CanReorderLanes = (IID != Intrinsic::vector_reduce_fadd &&
IID != Intrinsic::vector_reduce_fmul) ||
II->hasAllowReassoc();
const unsigned ArgIdx = (IID == Intrinsic::vector_reduce_fadd ||
IID == Intrinsic::vector_reduce_fmul)
? 1
: 0;
Value *Arg = II->getArgOperand(ArgIdx);
Value *V;
ArrayRef<int> Mask;
if (!isa<FixedVectorType>(Arg->getType()) || !CanBeReassociated ||
!match(Arg, m_Shuffle(m_Value(V), m_Undef(), m_Mask(Mask))) ||
!cast<ShuffleVectorInst>(Arg)->isSingleSource())
break;
int Sz = Mask.size();
SmallBitVector UsedIndices(Sz);
for (int Idx : Mask) {
if (Idx == PoisonMaskElem || UsedIndices.test(Idx))
break;
UsedIndices.set(Idx);
}
// Can remove shuffle iff just shuffled elements, no repeats, undefs, or
// other changes.
if (UsedIndices.all()) {
replaceUse(II->getOperandUse(ArgIdx), V);
if (Value *NewOp = simplifyReductionOperand(Arg, CanReorderLanes)) {
replaceUse(II->getOperandUse(ArgIdx), NewOp);
return nullptr;
}
break;
Expand Down
72 changes: 72 additions & 0 deletions llvm/test/Transforms/InstCombine/vector-logical-reductions.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -21,5 +21,77 @@ define i1 @reduction_logical_and(<4 x i1> %x) {
ret i1 %r
}

define i1 @reduction_logical_or_reverse_nxv2i1(<vscale x 2 x i1> %p) {
; CHECK-LABEL: @reduction_logical_or_reverse_nxv2i1(
; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[P:%.*]])
; CHECK-NEXT: ret i1 [[RED]]
;
%rev = call <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1> %p)
%red = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %rev)
ret i1 %red
}

define i1 @reduction_logical_or_reverse_v2i1(<2 x i1> %p) {
; CHECK-LABEL: @reduction_logical_or_reverse_v2i1(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[P:%.*]] to i2
; CHECK-NEXT: [[RED:%.*]] = icmp ne i2 [[TMP1]], 0
; CHECK-NEXT: ret i1 [[RED]]
;
%rev = call <2 x i1> @llvm.vector.reverse.v2i1(<2 x i1> %p)
%red = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %rev)
ret i1 %red
}

define i1 @reduction_logical_and_reverse_nxv2i1(<vscale x 2 x i1> %p) {
; CHECK-LABEL: @reduction_logical_and_reverse_nxv2i1(
; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> [[P:%.*]])
; CHECK-NEXT: ret i1 [[RED]]
;
%rev = call <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1> %p)
%red = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> %rev)
ret i1 %red
}

define i1 @reduction_logical_and_reverse_v2i1(<2 x i1> %p) {
; CHECK-LABEL: @reduction_logical_and_reverse_v2i1(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[P:%.*]] to i2
; CHECK-NEXT: [[RED:%.*]] = icmp eq i2 [[TMP1]], -1
; CHECK-NEXT: ret i1 [[RED]]
;
%rev = call <2 x i1> @llvm.vector.reverse.v2i1(<2 x i1> %p)
%red = call i1 @llvm.vector.reduce.and.v2i1(<2 x i1> %rev)
ret i1 %red
}

define i1 @reduction_logical_xor_reverse_nxv2i1(<vscale x 2 x i1> %p) {
; CHECK-LABEL: @reduction_logical_xor_reverse_nxv2i1(
; CHECK-NEXT: [[RED:%.*]] = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> [[P:%.*]])
; CHECK-NEXT: ret i1 [[RED]]
;
%rev = call <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1> %p)
%red = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> %rev)
ret i1 %red
}

define i1 @reduction_logical_xor_reverse_v2i1(<2 x i1> %p) {
; CHECK-LABEL: @reduction_logical_xor_reverse_v2i1(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i1> [[P:%.*]] to i2
; CHECK-NEXT: [[TMP2:%.*]] = call range(i2 0, -1) i2 @llvm.ctpop.i2(i2 [[TMP1]])
; CHECK-NEXT: [[RED:%.*]] = trunc i2 [[TMP2]] to i1
; CHECK-NEXT: ret i1 [[RED]]
;
%rev = call <2 x i1> @llvm.vector.reverse.v2i1(<2 x i1> %p)
%red = call i1 @llvm.vector.reduce.xor.v2i1(<2 x i1> %rev)
ret i1 %red
}

declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>)
declare i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1>)
declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1>)
declare i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1>)
declare i1 @llvm.vector.reduce.and.v2i1(<2 x i1>)
declare i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1>)
declare i1 @llvm.vector.reduce.xor.v2i1(<2 x i1>)
declare <vscale x 2 x i1> @llvm.vector.reverse.nxv2i1(<vscale x 2 x i1>)
declare <2 x i1> @llvm.vector.reverse.v2i1(<2 x i1>)
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