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[AMDGPU] Combine build_vector patterns for i16 and f16. NFCI. #91806

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Merged
merged 3 commits into from
May 10, 2024
Merged

[AMDGPU] Combine build_vector patterns for i16 and f16. NFCI. #91806

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8bb7683
[AMDGPU] Combine build_vector patterns for i16 and f16. NFCI.
rampitec May 10, 2024
f5e8e2e
Use vecTy.ElementType instead of switch
rampitec May 10, 2024
35ea606
Merge branch 'main' into combine-build-vector-patterns
rampitec May 10, 2024
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51 changes: 17 additions & 34 deletions llvm/lib/Target/AMDGPU/SIInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3166,49 +3166,33 @@ def : GCNPat <
(v2f16 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), VGPR_32:$src1))
>;

def : GCNPat <
(v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 undef))),
(COPY_TO_REGCLASS SReg_32:$src0, SReg_32)
>;

def : GCNPat <
(v2i16 (DivergentBinFrag<build_vector> (i16 VGPR_32:$src0), (i16 undef))),
(COPY_TO_REGCLASS VGPR_32:$src0, VGPR_32)
>;
foreach vecTy = [v2i16, v2f16] in {

def : GCNPat <
(v2f16 (build_vector f16:$src0, (f16 undef))),
(COPY $src0)
>;
defvar Ty = vecTy.ElementType;

def : GCNPat <
(v2i16 (UniformBinFrag<build_vector> (i16 undef), (i16 SReg_32:$src1))),
(S_LSHL_B32 SReg_32:$src1, (i32 16))
(vecTy (UniformBinFrag<build_vector> (Ty SReg_32:$src0), (Ty undef))),
(COPY_TO_REGCLASS SReg_32:$src0, SReg_32)
>;

def : GCNPat <
(v2i16 (DivergentBinFrag<build_vector> (i16 undef), (i16 VGPR_32:$src1))),
(v2i16 (V_LSHLREV_B32_e64 (i32 16), VGPR_32:$src1))
(vecTy (DivergentBinFrag<build_vector> (Ty VGPR_32:$src0), (Ty undef))),
(COPY_TO_REGCLASS VGPR_32:$src0, VGPR_32)
>;


def : GCNPat <
(v2f16 (UniformBinFrag<build_vector> (f16 undef), (f16 SReg_32:$src1))),
(vecTy (UniformBinFrag<build_vector> (Ty undef), (Ty SReg_32:$src1))),
(S_LSHL_B32 SReg_32:$src1, (i32 16))
>;

def : GCNPat <
(v2f16 (DivergentBinFrag<build_vector> (f16 undef), (f16 VGPR_32:$src1))),
(v2f16 (V_LSHLREV_B32_e64 (i32 16), VGPR_32:$src1))
(vecTy (DivergentBinFrag<build_vector> (Ty undef), (Ty VGPR_32:$src1))),
(vecTy (V_LSHLREV_B32_e64 (i32 16), VGPR_32:$src1))
>;
} // End foreach Ty = ...
}

let SubtargetPredicate = HasVOP3PInsts in {
def : GCNPat <
(v2i16 (UniformBinFrag<build_vector> (i16 SReg_32:$src0), (i16 SReg_32:$src1))),
(S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)
>;

def : GCNPat <
(v2i16 (DivergentBinFrag<build_vector> (i16 VGPR_32:$src0), (i16 VGPR_32:$src1))),
(v2i16 (V_LSHL_OR_B32_e64 $src1, (i32 16), (i32 (V_AND_B32_e64 (i32 (V_MOV_B32_e32 (i32 0xffff))), $src0))))
Expand All @@ -3227,18 +3211,17 @@ def : GCNPat <
(S_PACK_HH_B32_B16 SReg_32:$src0, SReg_32:$src1)
>;

def : GCNPat <
(v2f16 (UniformBinFrag<build_vector> (f16 SReg_32:$src0), (f16 SReg_32:$src1))),
(S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)
>;

foreach vecTy = [v2i16, v2f16] in {


foreach Ty = [i16, f16] in {

defvar vecTy = !if(!eq(Ty, i16), v2i16, v2f16);
defvar Ty = vecTy.ElementType;
defvar immzeroTy = !if(!eq(Ty, i16), immzero, fpimmzero);

def : GCNPat <
(vecTy (UniformBinFrag<build_vector> (Ty SReg_32:$src0), (Ty SReg_32:$src1))),
(S_PACK_LL_B32_B16 SReg_32:$src0, SReg_32:$src1)
>;

// Take the lower 16 bits from each VGPR_32 and concat them
def : GCNPat <
(vecTy (DivergentBinFrag<build_vector> (Ty VGPR_32:$a), (Ty VGPR_32:$b))),
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