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[DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on type mismatch #92195

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Merged
merged 3 commits into from
May 15, 2024
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[DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on type mismatch #92195

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[DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on undef or typ…
patrick-rivos May 14, 2024
064a084
fixup! [DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on undef…
patrick-rivos May 15, 2024
46104b6
fixup! [DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on undef…
patrick-rivos May 15, 2024
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7 changes: 5 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -12142,8 +12142,11 @@ SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) {
SDValue N2Elt = N2.getOperand(i);
if (N1Elt.isUndef() || N2Elt.isUndef())
continue;
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This loop may have been trying to ignore undefs.

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Updated. This invalidates the assertion I added (since a vector of undefs can be both AllAddOne and AllSubOne) so I removed that as well.

if (N1Elt.getValueType() != N2Elt.getValueType())
continue;
if (N1Elt.getValueType() != N2Elt.getValueType()) {
AllAddOne = false;
AllSubOne = false;
break;
}

const APInt &C1 = N1Elt->getAsAPIntVal();
const APInt &C2 = N2Elt->getAsAPIntVal();
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21 changes: 21 additions & 0 deletions llvm/test/CodeGen/RISCV/pr92193.ll
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@@ -0,0 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=riscv64-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -mtriple=riscv32-unknown-linux-gnu < %s | FileCheck %s

; Dag-combine used to improperly combine a vector vselect of 0 and 2 into
; 2 + condition(0/1) because one of the two args was transformed from an i32->i64.

define i16 @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
entry:
%insert.0 = insertelement <4 x i16> zeroinitializer, i16 2, i64 0
%all.two = shufflevector <4 x i16> %insert.0, <4 x i16> zeroinitializer, <4 x i32> zeroinitializer
%sel.0 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> zeroinitializer, <4 x i16> %all.two
%mul.0 = call i16 @llvm.vector.reduce.mul.v4i16(<4 x i16> %sel.0)
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Is the reduce needed? Can we hit the error by returning %sel.0?

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We don't seem to hit the error when returning %sel.0 (comments generated by llc with this PR applied):
https://godbolt.org/z/z7exjrYsc

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Thanks for checking

ret i16 %mul.0
}

declare i16 @llvm.vector.reduce.mul.v4i32(<4 x i16>)
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