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[SDAG][X86] Extend SplitVecOp_VSETCC for STRICT_FSETCC. #92509

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Merged
merged 3 commits into from
May 20, 2024
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[SDAG][X86] Extend SplitVecOp_VSETCC for STRICT_FSETCC. #92509

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0eac816
[SDAG][X86] Extend SplitVecOp_VSETCC for STRICT_FSETCC.
FreddyLeaf May 17, 2024
b8b0bc6
copy error
FreddyLeaf May 17, 2024
7ff5d8d
address comments.
FreddyLeaf May 17, 2024
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19 changes: 16 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3033,6 +3033,7 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
"operand!\n");

case ISD::VP_SETCC:
case ISD::STRICT_FSETCC:
case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
Expand Down Expand Up @@ -3997,14 +3998,16 @@ SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
}

SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
bool isStrict = N->getOpcode() == ISD::STRICT_FSETCC;
assert(N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() &&
N->getOperand(isStrict ? 1 : 0).getValueType().isVector() &&
"Operand types must be vectors");
// The result has a legal vector type, but the input needs splitting.
SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
SDLoc DL(N);
GetSplitVector(N->getOperand(0), Lo0, Hi0);
GetSplitVector(N->getOperand(1), Lo1, Hi1);
GetSplitVector(N->getOperand(isStrict ? 1 : 0), Lo0, Hi0);
GetSplitVector(N->getOperand(isStrict ? 2 : 1), Lo1, Hi1);

auto PartEltCnt = Lo0.getValueType().getVectorElementCount();

LLVMContext &Context = *DAG.getContext();
Expand All @@ -4014,6 +4017,16 @@ SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
if (N->getOpcode() == ISD::SETCC) {
LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
} else if (N->getOpcode() == ISD::STRICT_FSETCC) {
LoRes = DAG.getNode(ISD::STRICT_FSETCC, DL,
DAG.getVTList(PartResVT, N->getValueType(1)),
N->getOperand(0), Lo0, Lo1, N->getOperand(3));
HiRes = DAG.getNode(ISD::STRICT_FSETCC, DL,
DAG.getVTList(PartResVT, N->getValueType(1)),
N->getOperand(0), Hi0, Hi1, N->getOperand(3));
SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
LoRes.getValue(1), HiRes.getValue(1));
ReplaceValueWith(SDValue(N, 1), NewChain);
} else {
assert(N->getOpcode() == ISD::VP_SETCC && "Expected VP_SETCC opcode");
SDValue MaskLo, MaskHi, EVLLo, EVLHi;
Expand Down
40 changes: 40 additions & 0 deletions llvm/test/CodeGen/X86/vec-strict-cmp-512-skx.ll
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@@ -0,0 +1,40 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64 -mcpu=skx | FileCheck %s --check-prefixes=SKX

;; Test no crash for AVX512 targets without prefer-vector-width=512.

define <16 x i32> @test_v16f32_oeq_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
; SKX-LABEL: test_v16f32_oeq_q:
; SKX: # %bb.0:
; SKX-NEXT: vcmpeqps %ymm7, %ymm5, %k1
; SKX-NEXT: vcmpeqps %ymm6, %ymm4, %k2
; SKX-NEXT: vpblendmd %ymm0, %ymm2, %ymm0 {%k2}
; SKX-NEXT: vpblendmd %ymm1, %ymm3, %ymm1 {%k1}
; SKX-NEXT: retq
%cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
<16 x float> %f1, <16 x float> %f2, metadata !"oeq",
metadata !"fpexcept.strict") #0
%res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
ret <16 x i32> %res
}

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Test more vector types

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7ff5d8d

define <8 x i32> @test_v8f64_oeq_q(<8 x i32> %a, <8 x i32> %b, <8 x double> %f1, <8 x double> %f2) #0 {
; SKX-LABEL: test_v8f64_oeq_q:
; SKX: # %bb.0:
; SKX-NEXT: vcmpeqpd %ymm4, %ymm2, %k0
; SKX-NEXT: vcmpeqpd %ymm5, %ymm3, %k1
; SKX-NEXT: kshiftlb $4, %k1, %k1
; SKX-NEXT: korb %k1, %k0, %k1
; SKX-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
; SKX-NEXT: retq
%cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
<8 x double> %f1, <8 x double> %f2, metadata !"oeq",
metadata !"fpexcept.strict") #0
%res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
ret <8 x i32> %res
}

declare <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float>, <16 x float>, metadata, metadata)
declare <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double>, <8 x double>, metadata, metadata)

attributes #0 = { nounwind strictfp "min-legal-vector-width"="0" }
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