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X86: Fix asserting on bfloat argument/return without sse2 #93146

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Merged
merged 7 commits into from
Sep 30, 2024
Merged

X86: Fix asserting on bfloat argument/return without sse2 #93146

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db013ec
X86: Fix asserting on bfloat argument/return without sse2
arsenm May 23, 2024
def758c
Add nounwind
arsenm May 23, 2024
93097b0
Fix new test
arsenm May 29, 2024
54c7ce2
Remove bfloat ABI workaround in atomic test
arsenm May 29, 2024
ce08725
Merge branch 'main' into x86-calling-conv-bfloat-assert
arsenm Jul 31, 2024
1251656
Merge branch 'main' into x86-calling-conv-bfloat-assert
arsenm Sep 6, 2024
c19c738
Merge branch 'main' into x86-calling-conv-bfloat-assert
arsenm Sep 30, 2024
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18 changes: 11 additions & 7 deletions llvm/lib/Target/X86/X86ISelLoweringCall.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -124,12 +124,14 @@ MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
!Subtarget.hasX87())
return MVT::i32;

if (VT.isVector() && VT.getVectorElementType() == MVT::bf16)
return getRegisterTypeForCallingConv(Context, CC,
VT.changeVectorElementType(MVT::f16));
if (isTypeLegal(MVT::f16)) {
if (VT.isVector() && VT.getVectorElementType() == MVT::bf16)
return getRegisterTypeForCallingConv(
Context, CC, VT.changeVectorElementType(MVT::f16));

if (VT == MVT::bf16)
return MVT::f16;
if (VT == MVT::bf16)
return MVT::f16;
}

return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
}
Expand Down Expand Up @@ -162,7 +164,8 @@ unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
return 3;
}

if (VT.isVector() && VT.getVectorElementType() == MVT::bf16)
if (VT.isVector() && VT.getVectorElementType() == MVT::bf16 &&
isTypeLegal(MVT::f16))
return getNumRegistersForCallingConv(Context, CC,
VT.changeVectorElementType(MVT::f16));

Expand Down Expand Up @@ -194,7 +197,8 @@ unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
}

// Split vNbf16 vectors according to vNf16.
if (VT.isVector() && VT.getVectorElementType() == MVT::bf16)
if (VT.isVector() && VT.getVectorElementType() == MVT::bf16 &&
isTypeLegal(MVT::f16))
VT = VT.changeVectorElementType(MVT::f16);

return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
Expand Down
85 changes: 55 additions & 30 deletions llvm/test/CodeGen/X86/atomic-non-integer.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -789,12 +789,55 @@ define double @load_double_seq_cst(ptr %fptr) {
}

define void @store_bfloat(ptr %fptr, bfloat %v) {
; X86-LABEL: store_bfloat:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movw %cx, (%eax)
; X86-NEXT: retl
; X86-SSE1-LABEL: store_bfloat:
; X86-SSE1: # %bb.0:
; X86-SSE1-NEXT: pushl %esi
; X86-SSE1-NEXT: .cfi_def_cfa_offset 8
; X86-SSE1-NEXT: subl $8, %esp
; X86-SSE1-NEXT: .cfi_def_cfa_offset 16
; X86-SSE1-NEXT: .cfi_offset %esi, -8
; X86-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE1-NEXT: movss %xmm0, (%esp)
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE1-NEXT: calll __truncsfbf2
; X86-SSE1-NEXT: movw %ax, (%esi)
; X86-SSE1-NEXT: addl $8, %esp
; X86-SSE1-NEXT: .cfi_def_cfa_offset 8
; X86-SSE1-NEXT: popl %esi
; X86-SSE1-NEXT: .cfi_def_cfa_offset 4
; X86-SSE1-NEXT: retl
;
; X86-SSE2-LABEL: store_bfloat:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-SSE2-NEXT: movw %cx, (%eax)
; X86-SSE2-NEXT: retl
;
; X86-AVX-LABEL: store_bfloat:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movw %cx, (%eax)
; X86-AVX-NEXT: retl
;
; X86-NOSSE-LABEL: store_bfloat:
; X86-NOSSE: # %bb.0:
; X86-NOSSE-NEXT: pushl %esi
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
; X86-NOSSE-NEXT: subl $8, %esp
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 16
; X86-NOSSE-NEXT: .cfi_offset %esi, -8
; X86-NOSSE-NEXT: flds {{[0-9]+}}(%esp)
; X86-NOSSE-NEXT: fstps (%esp)
; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NOSSE-NEXT: calll __truncsfbf2
; X86-NOSSE-NEXT: movw %ax, (%esi)
; X86-NOSSE-NEXT: addl $8, %esp
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 8
; X86-NOSSE-NEXT: popl %esi
; X86-NOSSE-NEXT: .cfi_def_cfa_offset 4
; X86-NOSSE-NEXT: retl
;
; X64-SSE-LABEL: store_bfloat:
; X64-SSE: # %bb.0:
Expand All @@ -811,8 +854,7 @@ define void @store_bfloat(ptr %fptr, bfloat %v) {
ret void
}
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why is this codegen so poor vs store_half?

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It's ABI promotes to float vs. ABI promotes to i16


; Work around issue #92899 by casting to float
define float @load_bfloat(ptr %fptr) {
define bfloat @load_bfloat(ptr %fptr) {
; X86-SSE1-LABEL: load_bfloat:
; X86-SSE1: # %bb.0:
; X86-SSE1-NEXT: pushl %eax
Expand All @@ -828,30 +870,16 @@ define float @load_bfloat(ptr %fptr) {
;
; X86-SSE2-LABEL: load_bfloat:
; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %eax
; X86-SSE2-NEXT: .cfi_def_cfa_offset 8
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movzwl (%eax), %eax
; X86-SSE2-NEXT: shll $16, %eax
; X86-SSE2-NEXT: movd %eax, %xmm0
; X86-SSE2-NEXT: movd %xmm0, (%esp)
; X86-SSE2-NEXT: flds (%esp)
; X86-SSE2-NEXT: popl %eax
; X86-SSE2-NEXT: .cfi_def_cfa_offset 4
; X86-SSE2-NEXT: pinsrw $0, %eax, %xmm0
; X86-SSE2-NEXT: retl
;
; X86-AVX-LABEL: load_bfloat:
; X86-AVX: # %bb.0:
; X86-AVX-NEXT: pushl %eax
; X86-AVX-NEXT: .cfi_def_cfa_offset 8
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movzwl (%eax), %eax
; X86-AVX-NEXT: shll $16, %eax
; X86-AVX-NEXT: vmovd %eax, %xmm0
; X86-AVX-NEXT: vmovd %xmm0, (%esp)
; X86-AVX-NEXT: flds (%esp)
; X86-AVX-NEXT: popl %eax
; X86-AVX-NEXT: .cfi_def_cfa_offset 4
; X86-AVX-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
; X86-AVX-NEXT: retl
;
; X86-NOSSE-LABEL: load_bfloat:
Expand All @@ -870,17 +898,14 @@ define float @load_bfloat(ptr %fptr) {
; X64-SSE-LABEL: load_bfloat:
; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movzwl (%rdi), %eax
; X64-SSE-NEXT: shll $16, %eax
; X64-SSE-NEXT: movd %eax, %xmm0
; X64-SSE-NEXT: pinsrw $0, %eax, %xmm0
; X64-SSE-NEXT: retq
;
; X64-AVX-LABEL: load_bfloat:
; X64-AVX: # %bb.0:
; X64-AVX-NEXT: movzwl (%rdi), %eax
; X64-AVX-NEXT: shll $16, %eax
; X64-AVX-NEXT: vmovd %eax, %xmm0
; X64-AVX-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
; X64-AVX-NEXT: retq
%v = load atomic bfloat, ptr %fptr unordered, align 2
%ext = fpext bfloat %v to float
ret float %ext
ret bfloat %v
}
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