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[SCEV] Don't add predicates already implied by UnionPredicate. #93397

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Merged
merged 4 commits into from
May 27, 2024
Merged

[SCEV] Don't add predicates already implied by UnionPredicate. #93397

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7d6ae5b
[LV] Add test showing missed removal of implied predicate.
fhahn May 25, 2024
fbf7d4b
[SCEV] Don't add predicates already implied by UnionPredicate.
fhahn May 25, 2024
6208f38
Merge remote-tracking branch 'origin/main' into scev-union-pred-implied
fhahn May 27, 2024
8c2589a
!fixup address comments, thanks!
fhahn May 27, 2024
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4 changes: 3 additions & 1 deletion llvm/lib/Analysis/ScalarEvolution.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14751,7 +14751,9 @@ void SCEVUnionPredicate::add(const SCEVPredicate *N) {
return;
}

Preds.push_back(N);
// Only add predicate if it is not already implied by this union predicate.
if (!implies(N))
Preds.push_back(N);
}

PredicatedScalarEvolution::PredicatedScalarEvolution(ScalarEvolution &SE,
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33 changes: 13 additions & 20 deletions llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
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Expand Up @@ -152,7 +152,6 @@ for.end: ; preds = %for.cond

@h = global i64 0

; TODO: Currently we generate SCEV check code for the same predicate twice.
define void @implied_wrap_predicate(ptr %A, ptr %B, ptr %C) {
; CHECK-LABEL: define void @implied_wrap_predicate
; CHECK-SAME: (ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) {
Expand Down Expand Up @@ -184,17 +183,11 @@ define void @implied_wrap_predicate(ptr %A, ptr %B, ptr %C) {
; CHECK-NEXT: [[TMP16:%.*]] = icmp ult i16 [[TMP15]], 2
; CHECK-NEXT: [[TMP17:%.*]] = icmp ugt i64 [[TMP8]], 65535
; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP16]], [[TMP17]]
; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP8]] to i16
; CHECK-NEXT: [[TMP20:%.*]] = add i16 1, [[TMP19]]
; CHECK-NEXT: [[TMP21:%.*]] = icmp ult i16 [[TMP20]], 1
; CHECK-NEXT: [[TMP22:%.*]] = icmp ugt i64 [[TMP8]], 65535
; CHECK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
; CHECK-NEXT: [[TMP24:%.*]] = or i1 [[TMP13]], [[TMP18]]
; CHECK-NEXT: [[TMP25:%.*]] = or i1 [[TMP24]], [[TMP23]]
; CHECK-NEXT: br i1 [[TMP25]], label [[SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]]
; CHECK-NEXT: [[TMP19:%.*]] = or i1 [[TMP13]], [[TMP18]]
; CHECK-NEXT: br i1 [[TMP19]], label [[SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]]
; CHECK: vector.memcheck:
; CHECK-NEXT: [[TMP26:%.*]] = sub i64 [[C2]], [[A3]]
; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP26]], 32
; CHECK-NEXT: [[TMP20:%.*]] = sub i64 [[C2]], [[A3]]
; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP20]], 32
; CHECK-NEXT: br i1 [[DIFF_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP4]], 4
Expand All @@ -206,16 +199,16 @@ define void @implied_wrap_predicate(ptr %A, ptr %B, ptr %C) {
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]
; CHECK-NEXT: [[TMP27:%.*]] = add i64 [[OFFSET_IDX]], 0
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP27]]
; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i64, ptr [[TMP28]], i32 0
; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr [[TMP29]], align 4
; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP27]]
; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i64, ptr [[TMP30]], i32 0
; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr [[TMP31]], align 4
; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[OFFSET_IDX]], 0
; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP21]]
; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i64, ptr [[TMP22]], i32 0
; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr [[TMP23]], align 4
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP21]]
; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i64, ptr [[TMP24]], i32 0
; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr [[TMP25]], align 4
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP32:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP32]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP26]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: middle.block:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP4]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
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