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[ARM] Remove duplicate custom SDag node (NFCI) #93419

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Merged
merged 4 commits into from
Jun 15, 2024
Merged

[ARM] Remove duplicate custom SDag node (NFCI) #93419

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17b4347
[ARM] Remove duplicate custom SDag node (NFCI)
s-barannikov May 26, 2024
16ae102
Make clang-format happy
s-barannikov May 26, 2024
89e87ad
Merge branch 'main' into arm/subs
s-barannikov Jun 14, 2024
0ab8a69
Merge branch 'main' into arm/subs
s-barannikov Jun 15, 2024
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17 changes: 8 additions & 9 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -1715,7 +1715,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
MAKE_CASE(ARMISD::BCC_i64)
MAKE_CASE(ARMISD::FMSTAT)
MAKE_CASE(ARMISD::CMOV)
MAKE_CASE(ARMISD::SUBS)
MAKE_CASE(ARMISD::SSAT)
MAKE_CASE(ARMISD::USAT)
MAKE_CASE(ARMISD::ASRL)
Expand Down Expand Up @@ -18475,9 +18474,9 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
} else if (CC == ARMCC::NE && !isNullConstant(RHS) &&
(!Subtarget->isThumb1Only() || isPowerOf2Constant(TrueVal))) {
// This seems pointless but will allow us to combine it further below.
// CMOV 0, z, !=, (CMPZ x, y) -> CMOV (SUBS x, y), z, !=, (SUBS x, y):1
// CMOV 0, z, !=, (CMPZ x, y) -> CMOV (SUBC x, y), z, !=, (SUBC x, y):1
SDValue Sub =
DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
DAG.getNode(ARMISD::SUBC, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
Sub.getValue(1), SDValue());
Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, TrueVal, ARMcc,
Expand All @@ -18489,9 +18488,9 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
(!Subtarget->isThumb1Only() || isPowerOf2Constant(FalseVal))) {
// This seems pointless but will allow us to combine it further below
// Note that we change == for != as this is the dual for the case above.
// CMOV z, 0, ==, (CMPZ x, y) -> CMOV (SUBS x, y), z, !=, (SUBS x, y):1
// CMOV z, 0, ==, (CMPZ x, y) -> CMOV (SUBC x, y), z, !=, (SUBC x, y):1
SDValue Sub =
DAG.getNode(ARMISD::SUBS, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
DAG.getNode(ARMISD::SUBC, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS);
SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
Sub.getValue(1), SDValue());
Res = DAG.getNode(ARMISD::CMOV, dl, VT, Sub, FalseVal,
Expand All @@ -18503,21 +18502,21 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {

// On Thumb1, the DAG above may be further combined if z is a power of 2
// (z == 2 ^ K).
// CMOV (SUBS x, y), z, !=, (SUBS x, y):1 ->
// CMOV (SUBC x, y), z, !=, (SUBC x, y):1 ->
// t1 = (USUBO (SUB x, y), 1)
// t2 = (USUBO_CARRY (SUB x, y), t1:0, t1:1)
// Result = if K != 0 then (SHL t2:0, K) else t2:0
//
// This also handles the special case of comparing against zero; it's
// essentially, the same pattern, except there's no SUBS:
// essentially, the same pattern, except there's no SUBC:
// CMOV x, z, !=, (CMPZ x, 0) ->
// t1 = (USUBO x, 1)
// t2 = (USUBO_CARRY x, t1:0, t1:1)
// Result = if K != 0 then (SHL t2:0, K) else t2:0
const APInt *TrueConst;
if (Subtarget->isThumb1Only() && CC == ARMCC::NE &&
((FalseVal.getOpcode() == ARMISD::SUBS &&
FalseVal.getOperand(0) == LHS && FalseVal.getOperand(1) == RHS) ||
((FalseVal.getOpcode() == ARMISD::SUBC && FalseVal.getOperand(0) == LHS &&
FalseVal.getOperand(1) == RHS) ||
(FalseVal == LHS && isNullConstant(RHS))) &&
(TrueConst = isPowerOf2Constant(TrueVal))) {
SDVTList VTs = DAG.getVTList(VT, MVT::i32);
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/Target/ARM/ARMISelLowering.h
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Expand Up @@ -95,7 +95,6 @@ class VectorType;
FMSTAT, // ARM fmstat instruction.

CMOV, // ARM conditional move instructions.
SUBS, // Flag-setting subtraction.

SSAT, // Signed saturation
USAT, // Unsigned saturation
Expand Down Expand Up @@ -244,7 +243,7 @@ class VectorType;
VADDLVAps, // Same as VADDLVp[su] but with a v4i1 predicate mask
VADDLVApu,
VMLAVs, // sign- or zero-extend the elements of two vectors to i32, multiply
VMLAVu, // them and add the results together, returning an i32 of their sum
VMLAVu, // them and add the results together, returning an i32 of the sum
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clang-format insisted I change this line

VMLAVps, // Same as VMLAV[su] with a v4i1 predicate mask
VMLAVpu,
VMLALVs, // Same as VMLAV but with i64, returning the low and
Expand Down
9 changes: 0 additions & 9 deletions llvm/lib/Target/ARM/ARMInstrInfo.td
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Expand Up @@ -160,7 +160,6 @@ def ARMintretglue : SDNode<"ARMISD::INTRET_GLUE", SDT_ARMcall,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
[SDNPInGlue]>;
def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>;

def ARMssat : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>;

Expand Down Expand Up @@ -3879,14 +3878,6 @@ let isAdd = 1 in
defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>;
defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>;

def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>;
def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>;
def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift),
(SUBSrsi $Rn, so_reg_imm:$shift)>;
def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift),
(SUBSrsr $Rn, so_reg_reg:$shift)>;


let isAdd = 1 in
defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>;
defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>;
Expand Down
6 changes: 0 additions & 6 deletions llvm/lib/Target/ARM/ARMInstrThumb.td
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Expand Up @@ -1400,12 +1400,6 @@ let hasPostISelHook = 1, Defs = [CPSR] in {
Sched<[WriteALU]>;
}


def : T1Pat<(ARMsubs tGPR:$Rn, tGPR:$Rm), (tSUBSrr $Rn, $Rm)>;
def : T1Pat<(ARMsubs tGPR:$Rn, imm0_7:$imm3), (tSUBSi3 $Rn, imm0_7:$imm3)>;
def : T1Pat<(ARMsubs tGPR:$Rn, imm0_255:$imm8), (tSUBSi8 $Rn, imm0_255:$imm8)>;


// Sign-extend byte
def tSXTB : // A8.6.222
T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
Expand Down
6 changes: 0 additions & 6 deletions llvm/lib/Target/ARM/ARMInstrThumb2.td
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Expand Up @@ -2438,12 +2438,6 @@ defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>;
defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>;

def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_imm:$imm),
(t2SUBSri $Rn, t2_so_imm:$imm)>;
def : T2Pat<(ARMsubs GPRnopc:$Rn, rGPR:$Rm), (t2SUBSrr $Rn, $Rm)>;
def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
(t2SUBSrs $Rn, t2_so_reg:$ShiftedRm)>;

defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1, 1>;
defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube, 0, 1>;

Expand Down
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