[PowerPC] Adjust operand order of ADDItoc to be consistent with other ADDI* nodes

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

@@ -1079,13 +1079,13 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
     assert(IsAIX && TM.getCodeModel() == CodeModel::Small &&
            "PseudoOp only valid for small code model AIX");
 
-    // Transform %rN = ADDItoc/8 @op1, %r2.
+    // Transform %rN = ADDItoc/8 %r2, @op1.
     LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
 
     // Change the opcode to load address.
     TmpInst.setOpcode((!IsPPC64) ? (PPC::LA) : (PPC::LA8));
 
-    const MachineOperand &MO = MI->getOperand(1);
+    const MachineOperand &MO = MI->getOperand(2);
     assert(MO.isGlobal() && "Invalid operand for ADDItoc[8].");
 
     // Map the operand to its corresponding MCSymbol.
@@ -1094,7 +1094,6 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
     const MCExpr *Exp =
         MCSymbolRefExpr::create(MOSymbol, MCSymbolRefExpr::VK_None, OutContext);
 
-    TmpInst.getOperand(1) = TmpInst.getOperand(2);
     TmpInst.getOperand(2) = MCOperand::createExpr(Exp);
     EmitToStreamer(*OutStreamer, TmpInst);
     return;

llvm/lib/Target/PowerPC/PPCFastISel.cpp

@@ -2080,13 +2080,15 @@ unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
                       cast<GlobalVariable>(GV)->hasAttribute("toc-data");
 
   // For small code model, generate a simple TOC load.
-  if (CModel == CodeModel::Small)
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
-            IsAIXTocData ? TII.get(PPC::ADDItoc8) : TII.get(PPC::LDtoc),
-            DestReg)
-        .addGlobalAddress(GV)
-        .addReg(PPC::X2);
-  else {
+  if (CModel == CodeModel::Small) {
+    auto MIB = BuildMI(
+        *FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
+        IsAIXTocData ? TII.get(PPC::ADDItoc8) : TII.get(PPC::LDtoc), DestReg);
+    if (IsAIXTocData)
+      MIB.addReg(PPC::X2).addGlobalAddress(GV);
+    else
+      MIB.addGlobalAddress(GV).addReg(PPC::X2);
+  } else {
     // If the address is an externally defined symbol, a symbol with common
     // or externally available linkage, a non-local function address, or a
     // jump table address (not yet needed), or if we are generating code

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

@@ -6096,8 +6096,15 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
                                    EVT OperandTy) {
       SDValue GA = TocEntry->getOperand(0);
       SDValue TocBase = TocEntry->getOperand(1);
-      SDNode *MN = CurDAG->getMachineNode(OpCode, dl, OperandTy, GA, TocBase);
-      transferMemOperands(TocEntry, MN);
+      SDNode *MN = nullptr;
+      if (OpCode == PPC::ADDItoc || OpCode == PPC::ADDItoc8)
+        // toc-data access doesn't involve in loading from got, no need to
+        // keep memory operands.
+        MN = CurDAG->getMachineNode(OpCode, dl, OperandTy, TocBase, GA);
+      else {
+        MN = CurDAG->getMachineNode(OpCode, dl, OperandTy, GA, TocBase);
+        transferMemOperands(TocEntry, MN);
+      }
       ReplaceNode(TocEntry, MN);
     };
 

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

@@ -1485,11 +1485,9 @@ def ADDItocL8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:
 }
 
 // Local Data Transform
-def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
+def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
                    "#ADDItoc8",
-                   [(set i64:$rD,
-                     (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
-
+                   []>, isPPC64;
 let mayLoad = 1 in
 def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
                    "#LDtocL", []>, isPPC64;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

@@ -3347,10 +3347,8 @@ def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentr
                        [(set i32:$rD,
                          (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>;
 // TOC Data Transform on AIX
-def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
-                   "#ADDItoc",
-                   [(set i32:$rD,
-                     (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
+def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tocentry32:$disp),
+                   "#ADDItoc", []>;
 def ADDItocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp),
                    "#ADDItocL", []>;
 

llvm/test/CodeGen/PowerPC/toc-data-common.ll

@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s -DINSTR=lwz --check-prefix=CHECK
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s -DINSTR=ld --check-prefix=CHECK
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-64
 
 ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o
 ; RUN: llvm-objdump -t --symbol-description %t32.o | FileCheck %s --check-prefix=OBJ32
@@ -15,16 +15,28 @@
 
 define void @set(i32 noundef %_a) {
 ; CHECK-LABEL: set:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: la 4, a2[TD](2)
-; CHECK-NEXT: la 5, a1[TD](2)
-; CHECK-NEXT: stw 3, 0(4)
-; CHECK-NEXT: [[INSTR]] 4, L..C0(2) # @a4
-; CHECK-NEXT: stw 3, 0(5)
-; CHECK-NEXT: [[INSTR]] 5, L..C1(2) # @a3
-; CHECK-NEXT: stw 3, 0(4)
-; CHECK-NEXT: stw 3, 0(5)
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    la 4, a2[TD](2)
+; CHECK-NEXT:    lwz 5, L..C0(2) # @a4
+; CHECK-NEXT:    stw 3, 0(4)
+; CHECK-NEXT:    la 4, a1[TD](2)
+; CHECK-NEXT:    stw 3, 0(4)
+; CHECK-NEXT:    lwz 4, L..C1(2) # @a3
+; CHECK-NEXT:    stw 3, 0(5)
+; CHECK-NEXT:    stw 3, 0(4)
+; CHECK-NEXT:    blr
+;
+; CHECK-64-LABEL: set:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    la 4, a2[TD](2)
+; CHECK-64-NEXT:    ld 5, L..C0(2) # @a4
+; CHECK-64-NEXT:    stw 3, 0(4)
+; CHECK-64-NEXT:    la 4, a1[TD](2)
+; CHECK-64-NEXT:    stw 3, 0(4)
+; CHECK-64-NEXT:    ld 4, L..C1(2) # @a3
+; CHECK-64-NEXT:    stw 3, 0(5)
+; CHECK-64-NEXT:    stw 3, 0(4)
+; CHECK-64-NEXT:    blr
 entry:
 store i32 %_a, ptr @a2, align 4
 store i32 %_a, ptr @a1, align 4
@@ -35,80 +47,124 @@ ret void
 
 define i32 @get1() {
 ; CHECK-LABEL: get1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: la 3, a2[TD](2)
-; CHECK-NEXT: lwz 3, 0(3)
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    la 3, a2[TD](2)
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    blr
+;
+; CHECK-64-LABEL: get1:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    la 3, a2[TD](2)
+; CHECK-64-NEXT:    lwz 3, 0(3)
+; CHECK-64-NEXT:    blr
 entry:
 %0 = load i32, ptr @a2, align 4
 ret i32 %0
 }
 
 define i32 @get2() {
 ; CHECK-LABEL: get2:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: la 3, a1[TD](2)
-; CHECK-NEXT: lwz 3, 0(3)
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    la 3, a1[TD](2)
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    blr
+;
+; CHECK-64-LABEL: get2:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    la 3, a1[TD](2)
+; CHECK-64-NEXT:    lwz 3, 0(3)
+; CHECK-64-NEXT:    blr
 entry:
 %0 = load i32, ptr @a1, align 4
 ret i32 %0
 }
 
 define i32 @get3() {
 ; CHECK-LABEL: get3:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: [[INSTR]] 3, L..C0(2) # @a4
-; CHECK-NEXT: lwz 3, 0(3)
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, L..C0(2) # @a4
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    blr
+;
+; CHECK-64-LABEL: get3:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    ld 3, L..C0(2) # @a4
+; CHECK-64-NEXT:    lwz 3, 0(3)
+; CHECK-64-NEXT:    blr
 entry:
 %0 = load i32, ptr @a4, align 4
 ret i32 %0
 }
 
 define i32 @get4() {
 ; CHECK-LABEL: get4:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: [[INSTR]] 3, L..C1(2) # @a3
-; CHECK-NEXT: lwz 3, 0(3)
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, L..C1(2) # @a3
+; CHECK-NEXT:    lwz 3, 0(3)
+; CHECK-NEXT:    blr
+;
+; CHECK-64-LABEL: get4:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    ld 3, L..C1(2) # @a3
+; CHECK-64-NEXT:    lwz 3, 0(3)
+; CHECK-64-NEXT:    blr
 entry:
 %0 = load i32, ptr @a3, align 4
 ret i32 %0
 }
 
 define nonnull ptr @escape1() {
 ; CHECK-LABEL: escape1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: la 3, a2[TD](2)
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    la 3, a2[TD](2)
+; CHECK-NEXT:    blr
+;
+; CHECK-64-LABEL: escape1:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    la 3, a2[TD](2)
+; CHECK-64-NEXT:    blr
 entry:
 ret ptr @a2
 }
 
 define nonnull ptr @escape2() {
 ; CHECK-LABEL: escape2:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: la 3, a1[TD](2)
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    la 3, a1[TD](2)
+; CHECK-NEXT:    blr
+;
+; CHECK-64-LABEL: escape2:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    la 3, a1[TD](2)
+; CHECK-64-NEXT:    blr
 entry:
 ret ptr @a1
 }
 
 define nonnull ptr @escape3() {
 ; CHECK-LABEL: escape3:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: [[INSTR]] 3, L..C0(2) # @a4
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, L..C0(2) # @a4
+; CHECK-NEXT:    blr
+;
+; CHECK-64-LABEL: escape3:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    ld 3, L..C0(2) # @a4
+; CHECK-64-NEXT:    blr
 entry:
 ret ptr @a4
 }
 
 define nonnull ptr @escape4() {
 ; CHECK-LABEL: escape4:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: [[INSTR]] 3, L..C1(2) # @a3
-; CHECK-NEXT: blr
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwz 3, L..C1(2) # @a3
+; CHECK-NEXT:    blr
+;
+; CHECK-64-LABEL: escape4:
+; CHECK-64:       # %bb.0: # %entry
+; CHECK-64-NEXT:    ld 3, L..C1(2) # @a3
+; CHECK-64-NEXT:    blr
 entry:
 ret ptr @a3
 }

llvm/test/CodeGen/PowerPC/toc-data.ll

@@ -36,20 +36,20 @@ define dso_local void @write_int(i32 signext %in) {
     ret void
 }
 ; CHECK32: name:            write_int
-; CHECK32:      %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @i, $r2
+; CHECK32:      %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc $r2, @i
 ; CHECK32-NEXT: STW %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store (s32) into @i)
 
 ; TEST32:         .write_int:
 ; TEST32:           la 4, i[TD](2)
 ; TEST32-NEXT:      stw 3, 0(4)
 
 ; CHECK64: name:            write_int
-; CHECK64:      %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2
+; CHECK64:      %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 $x2, @i
 ; CHECK64-NEXT: STW8 %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store (s32) into @i)
 
 ; CHECK64-NOOPT:  name: write_int
 ; CHECK64-NOOPT:    %[[SUBREG:[0-9]+]]:gprc = COPY %{{[0-9]}}.sub_32
-; CHECK64-NOOPT:    %[[ADDR:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2
+; CHECK64-NOOPT:    %[[ADDR:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 $x2, @i
 ; CHECK64-NOOPT:    STW %[[SUBREG]], 0, %[[ADDR]]
 
 ; TEST64:         .write_int:
@@ -128,19 +128,19 @@ define dso_local float @read_float() {
     ret float %0
 }
 ; CHECK32: name:            read_float
-; CHECK32: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @f, $r2
+; CHECK32: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc $r2, @f
 ; CHECK32: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load (s32) from @f)
 
 ; TEST32:       .read_float:
 ; TEST32:         la 3, f[TD](2)
 ; TEST32-NEXT:    lfs 1, 0(3)
 
 ; CHECK64: name:            read_float
-; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @f, $x2
+; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 $x2, @f
 ; CHECK64: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load (s32) from @f)
 
 ; CHECK64-NOOPT: name:            read_float
-; CHECK64-NOOPT:   %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @f, $x2
+; CHECK64-NOOPT:   %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 $x2, @f
 ; CHECK64-NOOPT:   %{{[0-9]+}}:f4rc = LFS 0, %[[SCRATCH]]
 
 ; TEST64:       .read_float:
@@ -217,18 +217,18 @@ define dso_local nonnull ptr @addr() {
     ret ptr @i
 }
 ; CHECK32: name:            addr
-; CHECK32:       %[[SCRATCH:[0-9]+]]:gprc = ADDItoc @i, $r2
+; CHECK32:       %[[SCRATCH:[0-9]+]]:gprc = ADDItoc $r2, @i
 ; CHECK32-NEXT:  $r3 = COPY %[[SCRATCH]]
 
 ; TEST32:       .addr
 ; TEST32:         la 3, i[TD](2)
 
 ; CHECK64: name:            addr
-; CHECK64:       %[[SCRATCH:[0-9]+]]:g8rc = ADDItoc8 @i, $x2
+; CHECK64:       %[[SCRATCH:[0-9]+]]:g8rc = ADDItoc8 $x2, @i
 ; CHECK64-NEXT:  $x3 = COPY %[[SCRATCH]]
 
 ; CHECK64-NOOPT: name:            addr
-; CHECK64-NOOPT:   %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2
+; CHECK64-NOOPT:   %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 $x2, @i
 ; CHECK64-NOOPT:   $x3 = COPY %[[SCRATCH]]
 
 ; TEST64:       .addr