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[WebAssembly] Implement all f16x8 relation instructions. #93751

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May 30, 2024
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[WebAssembly] Implement all f16x8 relation instructions. #93751

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11 changes: 9 additions & 2 deletions llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
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Original file line number Diff line number Diff line change
Expand Up @@ -720,13 +720,19 @@ def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
// Comparisons
//===----------------------------------------------------------------------===//

multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop> {
multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop,
list<Predicate> reqs = []> {
defm _#vec :
SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
[(set (vec.int_vt V128:$dst),
(setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))],
vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
vec.prefix#"."#name, simdop>;
vec.prefix#"."#name, simdop, reqs>;
}

multiclass HalfPrecisionCondition<Vec vec, string name, CondCode cond,
bits<32> simdop> {
defm "" : SIMDCondition<vec, name, cond, simdop, [HasHalfPrecision]>;
}

multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> {
Expand All @@ -738,6 +744,7 @@ multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> {
multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
defm "" : SIMDCondition<F32x4, name, cond, baseInst>;
defm "" : SIMDCondition<F64x2, name, cond, !add(baseInst, 6)>;
defm "" : HalfPrecisionCondition<F16x8, name, cond, !add(baseInst, 255)>;
}

// Equality: eq
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54 changes: 54 additions & 0 deletions llvm/test/CodeGen/WebAssembly/half-precision.ll
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Expand Up @@ -103,3 +103,57 @@ define <8 x half> @pmax_intrinsic_v8f16(<8 x half> %a, <8 x half> %b) {
%v = call <8 x half> @llvm.wasm.pmax.v8f16(<8 x half> %a, <8 x half> %b)
ret <8 x half> %v
}

; CHECK-LABEL: compare_oeq_v8f16:
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We have many more combination of fcmp that https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/WebAssembly/simd-comparisons.ll tests. Do we assume that the semantics are the same with them?

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I would assume they'd be the same. I'll add some more tests.

; CHECK-NEXT: .functype compare_oeq_v8f16 (v128, v128) -> (v128){{$}}
; CHECK-NEXT: f16x8.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <8 x i1> @compare_oeq_v8f16 (<8 x half> %x, <8 x half> %y) {
%res = fcmp oeq <8 x half> %x, %y
ret <8 x i1> %res
}

; CHECK-LABEL: compare_une_v8f16:
; CHECK-NEXT: .functype compare_une_v8f16 (v128, v128) -> (v128){{$}}
; CHECK-NEXT: f16x8.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <8 x i1> @compare_une_v8f16 (<8 x half> %x, <8 x half> %y) {
%res = fcmp une <8 x half> %x, %y
ret <8 x i1> %res
}

; CHECK-LABEL: compare_olt_v8f16:
; CHECK-NEXT: .functype compare_olt_v8f16 (v128, v128) -> (v128){{$}}
; CHECK-NEXT: f16x8.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <8 x i1> @compare_olt_v8f16 (<8 x half> %x, <8 x half> %y) {
%res = fcmp olt <8 x half> %x, %y
ret <8 x i1> %res
}

; CHECK-LABEL: compare_ogt_v8f16:
; CHECK-NEXT: .functype compare_ogt_v8f16 (v128, v128) -> (v128){{$}}
; CHECK-NEXT: f16x8.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <8 x i1> @compare_ogt_v8f16 (<8 x half> %x, <8 x half> %y) {
%res = fcmp ogt <8 x half> %x, %y
ret <8 x i1> %res
}

; CHECK-LABEL: compare_ole_v8f16:
; CHECK-NEXT: .functype compare_ole_v8f16 (v128, v128) -> (v128){{$}}
; CHECK-NEXT: f16x8.le $push[[R:[0-9]+]]=, $0, $1{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <8 x i1> @compare_ole_v8f16 (<8 x half> %x, <8 x half> %y) {
%res = fcmp ole <8 x half> %x, %y
ret <8 x i1> %res
}

; CHECK-LABEL: compare_oge_v8f16:
; CHECK-NEXT: .functype compare_oge_v8f16 (v128, v128) -> (v128){{$}}
; CHECK-NEXT: f16x8.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
; CHECK-NEXT: return $pop[[R]]{{$}}
define <8 x i1> @compare_oge_v8f16 (<8 x half> %x, <8 x half> %y) {
%res = fcmp oge <8 x half> %x, %y
ret <8 x i1> %res
}
18 changes: 18 additions & 0 deletions llvm/test/MC/WebAssembly/simd-encodings.s
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Expand Up @@ -875,4 +875,22 @@ main:
# CHECK: f16x8.pmax # encoding: [0xfd,0xbb,0x02]
f16x8.pmax

# CHECK: f16x8.eq # encoding: [0xfd,0xc0,0x02]
f16x8.eq

# CHECK: f16x8.ne # encoding: [0xfd,0xc1,0x02]
f16x8.ne

# CHECK: f16x8.lt # encoding: [0xfd,0xc2,0x02]
f16x8.lt

# CHECK: f16x8.gt # encoding: [0xfd,0xc3,0x02]
f16x8.gt

# CHECK: f16x8.le # encoding: [0xfd,0xc4,0x02]
f16x8.le

# CHECK: f16x8.ge # encoding: [0xfd,0xc5,0x02]
f16x8.ge

end_function
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