[PowerPC] Remove DAG matching in ADDIStocHA

[bzEq]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-powerpc

Author: Kai Luo (bzEq)

Changes

TOC_ENTRY node is created with {GA, Reg} operands, the pattern in ADDIStocHA is inconsistent.

---

Full diff: https://github.com/llvm/llvm-project/pull/93905.diff

1 Files Affected:

• (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.td (+1-1)

diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index e3d6d2f094f2e..8697a98d7accb 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3345,7 +3345,7 @@ def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor
 def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp),
                        "#ADDIStocHA",
                        [(set i32:$rD,
-                         (PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>;
+                         (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
 // TOC Data Transform on AIX
 def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
                    "#ADDItoc",

[mandlebug]

Since we need to transform the PPCtoc_entry node into 2 new nodes for large code model we do the transformation directly in PPCDAGToDAGISel::Select and so the match pattern here isn't used and can be removed.

[chenzheng1030]

Do we confirm the pattern is not used? @bzEq I saw there are LIT changes...

[bzEq]

Yes, the scheudling is changed. Since the machineinstr succeeds the attributes from the source SDAG node from the pattern. If the pattern is removed, the machineinstr loses these attributes. For PPCtoc_entry, the attributes are

SDNPMayLoad, SDNPMemOperand

[chenzheng1030]

OK. I think marking ADDIStocHA without load/store attributes is the right behavior.

[mandlebug]

LGTM.