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[AMDGPU] Do not override PseudoInstr in FLAT Pseudo definitions. NFC. #94369

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Jun 4, 2024
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[AMDGPU] Do not override PseudoInstr in FLAT Pseudo definitions. NFC. #94369

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21 changes: 4 additions & 17 deletions llvm/lib/Target/AMDGPU/FLATInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ def ScratchSVAddr : ComplexPattern<iPTR, 3, "SelectScratchSVAddr", [], [SDNPWant
class FLAT_Pseudo<string opName, dag outs, dag ins,
string asmOps, list<dag> pattern=[]> :
InstSI<outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
SIMCInstr<NAME, SIEncodingFamily.NONE> {

let isPseudo = 1;
let isCodeGenOnly = 1;
Expand Down Expand Up @@ -218,7 +218,6 @@ class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
let mayLoad = 1;
let has_saddr = HasSaddr;
let enabled_saddr = EnableSaddr;
let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");

let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
Expand All @@ -239,7 +238,6 @@ class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
let has_vdst = 0;
let has_saddr = HasSaddr;
let enabled_saddr = EnableSaddr;
let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
}

multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
Expand All @@ -265,7 +263,6 @@ class FLAT_Global_Load_AddTid_Pseudo <string opName, RegisterClass regClass,
let has_vaddr = 0;
let has_saddr = 1;
let enabled_saddr = EnableSaddr;
let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");

let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
Expand Down Expand Up @@ -305,7 +302,6 @@ class FLAT_Global_Load_LDS_Pseudo <string opName, bit EnableSaddr = 0> : FLAT_Ps
let has_saddr = 1;
let enabled_saddr = EnableSaddr;
let VALU = 1;
let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
let Uses = [M0, EXEC];
let SchedRW = [WriteVMEM, WriteLDS];
}
Expand All @@ -331,7 +327,6 @@ class FLAT_Global_Store_AddTid_Pseudo <string opName, RegisterClass vdataClass,
let has_vaddr = 0;
let has_saddr = 1;
let enabled_saddr = EnableSaddr;
let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
}

multiclass FLAT_Global_Store_AddTid_Pseudo<string opName, RegisterClass regClass> {
Expand Down Expand Up @@ -401,7 +396,6 @@ class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
let has_vaddr = EnableVaddr;
let has_sve = EnableSVE;
let sve = EnableVaddr;
let PseudoInstr = opName#!if(EnableSVE, "_SVS", !if(EnableSaddr, "_SADDR", !if(EnableVaddr, "", "_ST")));

let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
Expand Down Expand Up @@ -430,7 +424,6 @@ class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit En
let has_vaddr = EnableVaddr;
let has_sve = EnableSVE;
let sve = EnableVaddr;
let PseudoInstr = opName#!if(EnableSVE, "_SVS", !if(EnableSaddr, "_SADDR", !if(EnableVaddr, "", "_ST")));
}

multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedOutput = 0> {
Expand Down Expand Up @@ -490,7 +483,6 @@ class FLAT_Scratch_Load_LDS_Pseudo <string opName, bit EnableSaddr = 0,
let has_sve = EnableSVE;
let sve = EnableVaddr;
let VALU = 1;
let PseudoInstr = opName#!if(EnableSVE, "_SVS", !if(EnableSaddr, "_SADDR", !if(EnableVaddr, "", "_ST")));
let Uses = [M0, EXEC];
let SchedRW = [WriteVMEM, WriteLDS];
}
Expand Down Expand Up @@ -528,7 +520,6 @@ class FLAT_AtomicRet_Pseudo<string opName, dag outs, dag ins,
let sccbValue = 0;
let IsAtomicNoRet = 0;
let IsAtomicRet = 1;
let PseudoInstr = NAME # "_RTN";
}

multiclass FLAT_Atomic_Pseudo_NO_RTN<
Expand All @@ -543,7 +534,6 @@ multiclass FLAT_Atomic_Pseudo_NO_RTN<
(ins VReg_64:$vaddr, data_op:$vdata, flat_offset:$offset, CPol_0:$cpol),
" $vaddr, $vdata$offset$cpol">,
GlobalSaddrTable<0, opName> {
let PseudoInstr = NAME;
let FPAtomic = data_vt.isFP;
let AddedComplexity = -1; // Prefer global atomics if available
}
Expand Down Expand Up @@ -592,7 +582,6 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
" $vaddr, $vdata, off$offset$cpol">,
GlobalSaddrTable<0, opName> {
let has_saddr = 1;
let PseudoInstr = NAME;
let FPAtomic = data_vt.isFP;
}

Expand All @@ -603,7 +592,6 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
GlobalSaddrTable<1, opName> {
let has_saddr = 1;
let enabled_saddr = 1;
let PseudoInstr = NAME#"_SADDR";
let FPAtomic = data_vt.isFP;
}
}
Expand Down Expand Up @@ -635,7 +623,6 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
GlobalSaddrTable<1, opName#"_rtn"> {
let has_saddr = 1;
let enabled_saddr = 1;
let PseudoInstr = NAME#"_SADDR_RTN";
let FPAtomic = data_vt.isFP;
}
}
Expand Down Expand Up @@ -1870,7 +1857,7 @@ multiclass FLAT_Real_AllAddr_SVE_vi<bits<7> op> {
}

multiclass FLAT_Real_AllAddr_LDS<bits<7> op, bits<7> pre_gfx940_op,
string pre_gfx940_name = !subst("_lds", "", !cast<FLAT_Pseudo>(NAME).PseudoInstr),
string pre_gfx940_name = !subst("_lds", "", !cast<FLAT_Pseudo>(NAME).Mnemonic),
bit has_sccb = !cast<FLAT_Pseudo>(NAME).has_sccb> {

let OtherPredicates = [isGFX8GFX9NotGFX940] in {
Expand Down Expand Up @@ -2165,7 +2152,7 @@ multiclass FLAT_Real_ScratchAllAddr_gfx10<bits<7> op> :
FLAT_Real_ST_gfx10<op>;

multiclass FLAT_Real_AllAddr_LDS_gfx10<bits<7> op,
string opname = !subst("_lds", "", !cast<FLAT_Pseudo>(NAME).PseudoInstr)> {
string opname = !subst("_lds", "", !cast<FLAT_Pseudo>(NAME).Mnemonic)> {
let AsmString = opname # !cast<FLAT_Pseudo>(NAME).AsmOperands # " lds" in
defm "" : FLAT_Real_Base_gfx10<op>;

Expand All @@ -2174,7 +2161,7 @@ multiclass FLAT_Real_AllAddr_LDS_gfx10<bits<7> op,
}

multiclass FLAT_Real_ScratchAllAddr_LDS_gfx10<bits<7> op,
string opname = !subst("_lds", "", !cast<FLAT_Pseudo>(NAME).PseudoInstr)> {
string opname = !subst("_lds", "", !cast<FLAT_Pseudo>(NAME).Mnemonic)> {
defm "" : FLAT_Real_AllAddr_LDS_gfx10<op>;

let AsmString = opname # !cast<FLAT_Pseudo>(NAME#"_ST").AsmOperands # " lds" in
Expand Down
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