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[RISCV] Remove VPseudoBinaryMOutNoMask. NFC #94531

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Merged
merged 1 commit into from
Jun 5, 2024

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topperc
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@topperc topperc commented Jun 5, 2024

It appears to be identical to VPseudoBinaryNoMask. The comment above it doesn't make sense since VPseudoBinaryNoMask doesn't restrict the destination register to not include V0. Looks like a copy/paste from VPseudoBinaryMOutMask.

It appears to be identical to VPseudoBinaryNoMask. The comment
above it doesn't make sense since VPseudoBinaryNoMask doesn't restrict
the destination register to not include V0. Looks like a copy/paste
from VPseudoBinaryMOutMask.
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llvmbot commented Jun 5, 2024

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

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It appears to be identical to VPseudoBinaryNoMask. The comment above it doesn't make sense since VPseudoBinaryNoMask doesn't restrict the destination register to not include V0. Looks like a copy/paste from VPseudoBinaryMOutMask.


Full diff: https://github.com/llvm/llvm-project/pull/94531.diff

1 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+2-20)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 5fe5a7a5bd5cc..e97048f5a90f0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1422,24 +1422,6 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
   let UsesVXRM = 0;
 }
 
-// Like VPseudoBinaryNoMask, but output can be V0.
-class VPseudoBinaryMOutNoMask<VReg RetClass,
-                              VReg Op1Class,
-                              DAGOperand Op2Class,
-                              string Constraint,
-                              int TargetConstraintType = 1> :
-      Pseudo<(outs RetClass:$rd),
-             (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
-      RISCVVPseudo {
-  let mayLoad = 0;
-  let mayStore = 0;
-  let hasSideEffects = 0;
-  let Constraints = Constraint;
-  let TargetOverlapConstraintType = TargetConstraintType;
-  let HasVLOp = 1;
-  let HasSEWOp = 1;
-}
-
 // Like VPseudoBinaryMask, but output can be V0.
 class VPseudoBinaryMOutMask<VReg RetClass,
                             RegisterClass Op1Class,
@@ -2172,8 +2154,8 @@ multiclass VPseudoBinaryM<VReg RetClass,
                           int TargetConstraintType = 1,
                           bit Commutable = 0> {
   let VLMul = MInfo.value, isCommutable = Commutable in {
-    def "_" # MInfo.MX : VPseudoBinaryMOutNoMask<RetClass, Op1Class, Op2Class,
-                                                 Constraint, TargetConstraintType>;
+    def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
+                                             Constraint, TargetConstraintType>;
     let ForceTailAgnostic = true in
     def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
                                                          Op2Class, Constraint, TargetConstraintType>,

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LGTM

@topperc topperc merged commit a9342f2 into llvm:main Jun 5, 2024
7 of 8 checks passed
@topperc topperc deleted the pr/remove-class branch June 5, 2024 22:46
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3 participants