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[SLP] NFC. Refactor and add getAltInstrMask help function. #94709

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merged 2 commits into from
Jun 25, 2024
Merged

[SLP] NFC. Refactor and add getAltInstrMask help function. #94709

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[SLP] NFC. Refactor and add getAltInstrMask help function.
HanKuanChen Jun 7, 2024
a43bc81
Update llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
HanKuanChen Jun 25, 2024
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29 changes: 14 additions & 15 deletions llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -983,6 +983,17 @@ static void fixupOrderingIndices(MutableArrayRef<unsigned> Order) {
}
}

/// \returns a bitset for selecting opcodes. false for Opcode0 and true for
/// Opcode1.
SmallBitVector getAltInstrMask(ArrayRef<Value *> VL, unsigned Opcode0,
unsigned Opcode1) {
SmallBitVector OpcodeMask(VL.size(), false);
for (unsigned Lane : seq<unsigned>(VL.size()))
if (cast<Instruction>(VL[Lane])->getOpcode() == Opcode1)
OpcodeMask.set(Lane);
return OpcodeMask;
}

namespace llvm {

static void inversePermutation(ArrayRef<unsigned> Indices,
Expand Down Expand Up @@ -5093,11 +5104,7 @@ void BoUpSLP::reorderTopToBottom() {
FixedVectorType::get(TE->Scalars[0]->getType(), TE->Scalars.size());
unsigned Opcode0 = TE->getOpcode();
unsigned Opcode1 = TE->getAltOpcode();
// The opcode mask selects between the two opcodes.
SmallBitVector OpcodeMask(TE->Scalars.size(), false);
for (unsigned Lane : seq<unsigned>(0, TE->Scalars.size()))
if (cast<Instruction>(TE->Scalars[Lane])->getOpcode() == Opcode1)
OpcodeMask.set(Lane);
SmallBitVector OpcodeMask(getAltInstrMask(TE->Scalars, Opcode0, Opcode1));
// If this pattern is supported by the target then we consider the order.
if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) {
VFToOrderedEntries[TE->getVectorFactor()].insert(TE.get());
Expand Down Expand Up @@ -6009,11 +6016,7 @@ bool BoUpSLP::areAltOperandsProfitable(const InstructionsState &S,
ArrayRef<Value *> VL) const {
unsigned Opcode0 = S.getOpcode();
unsigned Opcode1 = S.getAltOpcode();
// The opcode mask selects between the two opcodes.
SmallBitVector OpcodeMask(VL.size(), false);
for (unsigned Lane : seq<unsigned>(0, VL.size()))
if (cast<Instruction>(VL[Lane])->getOpcode() == Opcode1)
OpcodeMask.set(Lane);
SmallBitVector OpcodeMask(getAltInstrMask(VL, Opcode0, Opcode1));
// If this pattern is supported by the target then consider it profitable.
if (TTI->isLegalAltInstr(FixedVectorType::get(S.MainOp->getType(), VL.size()),
Opcode0, Opcode1, OpcodeMask))
Expand Down Expand Up @@ -9746,11 +9749,7 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef<Value *> VectorizedVals,
// order.
unsigned Opcode0 = E->getOpcode();
unsigned Opcode1 = E->getAltOpcode();
// The opcode mask selects between the two opcodes.
SmallBitVector OpcodeMask(E->Scalars.size(), false);
for (unsigned Lane : seq<unsigned>(0, E->Scalars.size()))
if (cast<Instruction>(E->Scalars[Lane])->getOpcode() == Opcode1)
OpcodeMask.set(Lane);
SmallBitVector OpcodeMask(getAltInstrMask(E->Scalars, Opcode0, Opcode1));
// If this pattern is supported by the target then we consider the
// order.
if (TTIRef.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) {
Expand Down
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