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Merged
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Jun 21, 2024
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[RISCV] Make M imply Zmmul #95070

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2 changes: 1 addition & 1 deletion clang/lib/Basic/Targets/RISCV.cpp
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Expand Up @@ -168,7 +168,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
Twine(getVersionValue(ExtInfo.Major, ExtInfo.Minor)));
}

if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul"))
if (ISAInfo->hasExtension("zmmul"))
Builder.defineMacro("__riscv_mul");

if (ISAInfo->hasExtension("m")) {
Expand Down
24 changes: 12 additions & 12 deletions clang/test/CodeGen/RISCV/riscv-func-attr-target.c
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Expand Up @@ -66,16 +66,16 @@ void test_rvv_f64_type_w_zve64d() {
}

//.
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,-relax,-zbb,-zfa" }
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,+zmmul,-relax,-zbb,-zfa" }
// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" }
// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa" }
// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" }
// Make sure we append negative features if we override the arch
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,-relax,-zfa" }
// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }
// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
// CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa" }
// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" }
// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" }
// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" }
10 changes: 5 additions & 5 deletions lld/test/ELF/lto/riscv-attributes.ll
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Expand Up @@ -10,10 +10,10 @@
; CHECK: BuildAttributes {
; CHECK-NEXT: FormatVersion: 0x41
; CHECK-NEXT: Section 1 {
; CHECK-NEXT: SectionLength: 70
; CHECK-NEXT: SectionLength: 79
; CHECK-NEXT: Vendor: riscv
; CHECK-NEXT: Tag: Tag_File (0x1)
; CHECK-NEXT: Size: 60
; CHECK-NEXT: Size: 69
; CHECK-NEXT: FileAttributes {
; CHECK-NEXT: Attribute {
; CHECK-NEXT: Tag: 4
Expand All @@ -30,18 +30,18 @@
; CHECK-NEXT: Attribute {
; CHECK-NEXT: Tag: 5
; CHECK-NEXT: TagName: arch
; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zbb1p0{{$}}
; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zbb1p0{{$}}
; CHECK-NEXT: }
; CHECK-NEXT: }
; CHECK-NEXT: }
; CHECK-NEXT: }

;--- 1.s
.attribute 4, 16
.attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
.attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zmmul1p0"
;--- 2.s
.attribute 4, 16
.attribute 5, "rv32i2p1_m2p0_f2p2_d2p2_zbb1p0"
.attribute 5, "rv32i2p1_m2p0_f2p2_d2p2_zbb1p0_zmmul1p0"
.attribute 6, 1

;--- a.ll
Expand Down
20 changes: 10 additions & 10 deletions lld/test/ELF/riscv-attributes.s
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Expand Up @@ -64,20 +64,20 @@
# UNKNOWN22: warning: unknown22a.o:(.riscv.attributes): invalid tag 0x16 at offset 0x10

# HDR: Name Type Address Off Size ES Flg Lk Inf Al
# HDR: .riscv.attributes RISCV_ATTRIBUTES 0000000000000000 000158 00003e 00 0 0 1{{$}}
# HDR: .riscv.attributes RISCV_ATTRIBUTES 0000000000000000 000158 000047 00 0 0 1{{$}}

# HDR: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
# HDR: LOAD 0x000000 0x0000000000010000 0x0000000000010000 0x000158 0x000158 R 0x1000
# HDR-NEXT: GNU_STACK 0x000000 0x0000000000000000 0x0000000000000000 0x000000 0x000000 RW 0
# HDR-NEXT: ATTRIBUTES 0x000158 0x0000000000000000 0x0000000000000000 0x00003e 0x00003e R 0x1{{$}}
# HDR-NEXT: ATTRIBUTES 0x000158 0x0000000000000000 0x0000000000000000 0x000047 0x000047 R 0x1{{$}}

# CHECK: BuildAttributes {
# CHECK-NEXT: FormatVersion: 0x41
# CHECK-NEXT: Section 1 {
# CHECK-NEXT: SectionLength: 61
# CHECK-NEXT: SectionLength: 70
# CHECK-NEXT: Vendor: riscv
# CHECK-NEXT: Tag: Tag_File (0x1)
# CHECK-NEXT: Size: 51
# CHECK-NEXT: Size: 60
# CHECK-NEXT: FileAttributes {
# CHECK-NEXT: Attribute {
# CHECK-NEXT: Tag: 4
Expand All @@ -88,7 +88,7 @@
# CHECK-NEXT: Attribute {
# CHECK-NEXT: Tag: 5
# CHECK-NEXT: TagName: arch
# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0{{$}}
# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0{{$}}
# CHECK-NEXT: }
# CHECK-NEXT: }
# CHECK-NEXT: }
Expand All @@ -97,10 +97,10 @@
# CHECK2: BuildAttributes {
# CHECK2-NEXT: FormatVersion: 0x41
# CHECK2-NEXT: Section 1 {
# CHECK2-NEXT: SectionLength: 104
# CHECK2-NEXT: SectionLength: 113
# CHECK2-NEXT: Vendor: riscv
# CHECK2-NEXT: Tag: Tag_File (0x1)
# CHECK2-NEXT: Size: 94
# CHECK2-NEXT: Size: 103
# CHECK2-NEXT: FileAttributes {
# CHECK2-NEXT: Attribute {
# CHECK2-NEXT: Tag: 4
Expand All @@ -127,7 +127,7 @@
# CHECK2-NEXT: Attribute {
# CHECK2-NEXT: Tag: 5
# CHECK2-NEXT: TagName: arch
# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}}
# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}}
# CHECK2-NEXT: }
# CHECK2-NEXT: }
# CHECK2-NEXT: }
Expand All @@ -152,12 +152,12 @@

#--- a.s
.attribute stack_align, 16
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zmmul1p0"
.attribute unaligned_access, 0

#--- b.s
.attribute stack_align, 16
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0"
.attribute arch, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zmmul1p0"
.attribute priv_spec, 2
.attribute priv_spec_minor, 2

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Expand Up @@ -305,7 +305,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE, G_CONSTANT_POOL})
.legalFor({p0});

if (ST.hasStdExtM() || ST.hasStdExtZmmul()) {
if (ST.hasStdExtZmmul()) {
getActionDefinitionsBuilder(G_MUL)
.legalFor({s32, sXLen})
.widenScalarToNextPow2(0)
Expand Down
20 changes: 9 additions & 11 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -171,23 +171,21 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;

// Multiply Extensions

def FeatureStdExtZmmul
: RISCVExtension<"zmmul", 1, 0,
"'Zmmul' (Integer Multiplication)">;
def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">,
AssemblerPredicate<(all_of FeatureStdExtZmmul),
"'Zmmul' (Integer Multiplication)">;

def FeatureStdExtM
: RISCVExtension<"m", 2, 0,
"'M' (Integer Multiplication and Division)">;
"'M' (Integer Multiplication and Division)",
[FeatureStdExtZmmul]>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<(all_of FeatureStdExtM),
"'M' (Integer Multiplication and Division)">;

def FeatureStdExtZmmul
: RISCVExtension<"zmmul", 1, 0,
"'Zmmul' (Integer Multiplication)">;

def HasStdExtMOrZmmul
: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul),
"'M' (Integer Multiplication and Division) or "
"'Zmmul' (Integer Multiplication)">;

// Atomic Extensions

def FeatureStdExtA
Expand Down
7 changes: 3 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Expand Up @@ -300,7 +300,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setLibcallName(RTLIB::MULO_I64, nullptr);
}

if (!Subtarget.hasStdExtM() && !Subtarget.hasStdExtZmmul()) {
if (!Subtarget.hasStdExtZmmul()) {
setOperationAction({ISD::MUL, ISD::MULHS, ISD::MULHU}, XLenVT, Expand);
if (RV64LegalI32 && Subtarget.is64Bit())
setOperationAction(ISD::MUL, MVT::i32, Promote);
Expand Down Expand Up @@ -21012,14 +21012,13 @@ bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned)
bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
SDValue C) const {
// Check integral scalar types.
const bool HasExtMOrZmmul =
Subtarget.hasStdExtM() || Subtarget.hasStdExtZmmul();
const bool HasZmmul = Subtarget.hasStdExtZmmul();
if (!VT.isScalarInteger())
return false;

// Omit the optimization if the sub target has the M extension and the data
// size exceeds XLen.
if (HasExtMOrZmmul && VT.getSizeInBits() > Subtarget.getXLen())
if (HasZmmul && VT.getSizeInBits() > Subtarget.getXLen())
return false;

if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Expand Up @@ -3695,7 +3695,7 @@ void RISCVInstrInfo::mulImm(MachineFunction &MF, MachineBasicBlock &MBB,
.addReg(ScaledRegister, RegState::Kill)
.addReg(DestReg, RegState::Kill)
.setMIFlag(Flag);
} else if (STI.hasStdExtM() || STI.hasStdExtZmmul()) {
} else if (STI.hasStdExtZmmul()) {
Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass);
movImm(MBB, II, DL, N, Amount, Flag);
BuildMI(MBB, II, DL, get(RISCV::MUL), DestReg)
Expand Down
20 changes: 10 additions & 10 deletions llvm/lib/Target/RISCV/RISCVInstrInfoM.td
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Expand Up @@ -24,7 +24,7 @@ def riscv_remuw : SDNode<"RISCVISD::REMUW", SDT_RISCVIntBinOpW>;
// Instructions
//===----------------------------------------------------------------------===//

let Predicates = [HasStdExtMOrZmmul] in {
let Predicates = [HasStdExtZmmul] in {
def MUL : ALU_rr<0b0000001, 0b000, "mul", Commutable=1>,
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
def MULH : ALU_rr<0b0000001, 0b001, "mulh", Commutable=1>,
Expand All @@ -33,7 +33,7 @@ def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">,
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
def MULHU : ALU_rr<0b0000001, 0b011, "mulhu", Commutable=1>,
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
} // Predicates = [HasStdExtMOrZmmul]
} // Predicates = [HasStdExtZmmul]

let Predicates = [HasStdExtM] in {
def DIV : ALU_rr<0b0000001, 0b100, "div">,
Expand All @@ -46,10 +46,10 @@ def REMU : ALU_rr<0b0000001, 0b111, "remu">,
Sched<[WriteIRem, ReadIRem, ReadIRem]>;
} // Predicates = [HasStdExtM]

let Predicates = [HasStdExtMOrZmmul, IsRV64], IsSignExtendingOpW = 1 in {
let Predicates = [HasStdExtZmmul, IsRV64], IsSignExtendingOpW = 1 in {
def MULW : ALUW_rr<0b0000001, 0b000, "mulw", Commutable=1>,
Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
} // Predicates = [HasStdExtMOrZmmul, IsRV64]
} // Predicates = [HasStdExtZmmul, IsRV64]

let Predicates = [HasStdExtM, IsRV64], IsSignExtendingOpW = 1 in {
def DIVW : ALUW_rr<0b0000001, 0b100, "divw">,
Expand All @@ -66,12 +66,12 @@ def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">,
// Pseudo-instructions and codegen patterns
//===----------------------------------------------------------------------===//

let Predicates = [HasStdExtMOrZmmul] in {
let Predicates = [HasStdExtZmmul] in {
def : PatGprGpr<mul, MUL>;
def : PatGprGpr<mulhs, MULH>;
def : PatGprGpr<mulhu, MULHU>;
def : PatGprGpr<riscv_mulhsu, MULHSU>;
} // Predicates = [HasStdExtMOrZmmul]
} // Predicates = [HasStdExtZmmul]

let Predicates = [HasStdExtM] in {
def : PatGprGpr<sdiv, DIV>;
Expand All @@ -81,7 +81,7 @@ def : PatGprGpr<urem, REMU>;
} // Predicates = [HasStdExtM]

// Select W instructions if only the lower 32-bits of the result are used.
let Predicates = [HasStdExtMOrZmmul, IsRV64] in
let Predicates = [HasStdExtZmmul, IsRV64] in
def : PatGprGpr<binop_allwusers<mul>, MULW>;

let Predicates = [HasStdExtM, IsRV64] in {
Expand All @@ -106,20 +106,20 @@ def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
(REMW GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtM, IsRV64]

let Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] in {
let Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba] in {
// Special case for calculating the full 64-bit product of a 32x32 unsigned
// multiply where the inputs aren't known to be zero extended. We can shift the
// inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
// zeroing the upper 32 bits.
def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
(MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
} // Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba]
} // Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba]

//===----------------------------------------------------------------------===//
// Experimental RV64 i32 legalization patterns.
//===----------------------------------------------------------------------===//

let Predicates = [HasStdExtMOrZmmul, IsRV64] in {
let Predicates = [HasStdExtZmmul, IsRV64] in {
def : PatGprGpr<mul, MULW, i32, i32>;
}

Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
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Expand Up @@ -183,7 +183,7 @@ let Predicates = [HasStdExtZcb] in
def C_ZEXT_B : RVZcArith_r<0b11000 , "c.zext.b">,
Sched<[WriteIALU, ReadIALU]>;

let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in
let Predicates = [HasStdExtZcb, HasStdExtZmmul] in
def C_MUL : CA_ALU<0b100111, 0b10, "c.mul", GPRC>,
Sched<[WriteIMul, ReadIMul, ReadIMul]>;

Expand Down Expand Up @@ -270,13 +270,13 @@ def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8ge32:$index),
} // DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt]...


let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in{
let Predicates = [HasStdExtZcb, HasStdExtZmmul] in{
def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
(C_MUL GPRC:$rs1, GPRC:$rs2)>;
let isCompressOnly = true in
def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
(C_MUL GPRC:$rs1, GPRC:$rs2)>;
} // Predicates = [HasStdExtZcb, HasStdExtMOrZmmul]
} // Predicates = [HasStdExtZcb, HasStdExtZmmul]

let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
def : CompressPat<(SEXT_B GPRC:$rs1, GPRC:$rs1),
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/attributes-module-flag.ll
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Expand Up @@ -3,8 +3,8 @@

; Test generation of ELF attribute from module metadata

; RV32: .attribute 5, "rv32i2p1_m2p0_zba1p0"
; RV64: .attribute 5, "rv64i2p1_m2p0_zba1p0"
; RV32: .attribute 5, "rv32i2p1_m2p0_zmmul1p0_zba1p0"
; RV64: .attribute 5, "rv64i2p1_m2p0_zmmul1p0_zba1p0"

define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
Expand Down
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