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[DAG] fold avgu(zext(x), zext(y)) -> zext(avgu(x, y)) #95134

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Merged
merged 5 commits into from
Jun 12, 2024
Merged

[DAG] fold avgu(zext(x), zext(y)) -> zext(avgu(x, y)) #95134

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4ef1f7b
fold avgu(zext(x), zext(y)) -> zext(avgu(x, y))
c8ef Jun 11, 2024
8e04c8e
check extend from same type; check the original type
c8ef Jun 11, 2024
f32b0c6
use m_BinOp instead of m_c_BinOp
c8ef Jun 12, 2024
4bf4ee4
fix & add test
c8ef Jun 12, 2024
aef62c5
add negative test
c8ef Jun 12, 2024
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17 changes: 17 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5236,6 +5236,23 @@ SDValue DAGCombiner::visitAVG(SDNode *N) {
return DAG.getNode(ISD::SRL, DL, VT, X,
DAG.getShiftAmountConstant(1, VT, DL));

// fold avgu(zext(x), zext(y)) -> zext(avgu(x, y))
SDValue A;
SDValue B;
if (sd_match(
N, m_BinOp(ISD::AVGFLOORU, m_ZExt(m_Value(A)), m_ZExt(m_Value(B)))) &&
A.getValueType() == B.getValueType() &&
hasOperation(ISD::AVGFLOORU, A.getValueType())) {
SDValue AvgFloorU = DAG.getNode(ISD::AVGFLOORU, DL, A.getValueType(), A, B);
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, AvgFloorU);
}
if (sd_match(
N, m_BinOp(ISD::AVGCEILU, m_ZExt(m_Value(A)), m_ZExt(m_Value(B)))) &&
A.getValueType() == B.getValueType() &&
hasOperation(ISD::AVGCEILU, A.getValueType())) {
SDValue AvgCeilU = DAG.getNode(ISD::AVGCEILU, DL, A.getValueType(), A, B);
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, AvgCeilU);
}
return SDValue();
}

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6 changes: 2 additions & 4 deletions llvm/test/CodeGen/AArch64/aarch64-known-bits-hadd.ll
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Expand Up @@ -9,9 +9,8 @@ declare <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>)
define <8 x i16> @haddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
; CHECK-LABEL: haddu_zext:
; CHECK: // %bb.0:
; CHECK-NEXT: uhadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret
%x0 = zext <8 x i8> %a0 to <8 x i16>
%x1 = zext <8 x i8> %a1 to <8 x i16>
Expand All @@ -23,9 +22,8 @@ define <8 x i16> @haddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
define <8 x i16> @rhaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
; CHECK-LABEL: rhaddu_zext:
; CHECK: // %bb.0:
; CHECK-NEXT: urhadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret
%x0 = zext <8 x i8> %a0 to <8 x i16>
%x1 = zext <8 x i8> %a1 to <8 x i16>
Expand Down
82 changes: 82 additions & 0 deletions llvm/test/CodeGen/AArch64/avg.ll
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@@ -0,0 +1,82 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=aarch64 < %s | FileCheck %s

define <16 x i16> @zext_avgflooru(<16 x i8> %a0, <16 x i8> %a1) {
; CHECK-LABEL: zext_avgflooru:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: uhadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: uhadd v1.8b, v2.8b, v3.8b
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: ret
%x0 = zext <16 x i8> %a0 to <16 x i16>
%x1 = zext <16 x i8> %a1 to <16 x i16>
%and = and <16 x i16> %x0, %x1
%xor = xor <16 x i16> %x0, %x1
%shift = lshr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%avg = add <16 x i16> %and, %shift
ret <16 x i16> %avg
}

define <16 x i16> @zext_avgflooru_negative(<16 x i8> %a0, <16 x i4> %a1) {
; CHECK-LABEL: zext_avgflooru_negative:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.16b, #15
; CHECK-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-NEXT: ext v2.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: uhadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: uhadd v1.8b, v3.8b, v2.8b
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: ret
%x0 = zext <16 x i8> %a0 to <16 x i16>
%x1 = zext <16 x i4> %a1 to <16 x i16>
%and = and <16 x i16> %x0, %x1
%xor = xor <16 x i16> %x0, %x1
%shift = lshr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%avg = add <16 x i16> %and, %shift
ret <16 x i16> %avg
}

define <16 x i16> @zext_avgceilu(<16 x i8> %a0, <16 x i8> %a1) {
; CHECK-LABEL: zext_avgceilu:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: urhadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: urhadd v1.8b, v2.8b, v3.8b
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: ret
%x0 = zext <16 x i8> %a0 to <16 x i16>
%x1 = zext <16 x i8> %a1 to <16 x i16>
%or = or <16 x i16> %x0, %x1
%xor = xor <16 x i16> %x0, %x1
%shift = lshr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%avg = sub <16 x i16> %or, %shift
ret <16 x i16> %avg
}

define <16 x i16> @zext_avgceilu_negative(<16 x i4> %a0, <16 x i8> %a1) {
; CHECK-LABEL: zext_avgceilu_negative:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.16b, #15
; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
; CHECK-NEXT: urhadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-NEXT: urhadd v1.8b, v2.8b, v3.8b
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: ret
%x0 = zext <16 x i4> %a0 to <16 x i16>
%x1 = zext <16 x i8> %a1 to <16 x i16>
%or = or <16 x i16> %x0, %x1
%xor = xor <16 x i16> %x0, %x1
%shift = lshr <16 x i16> %xor, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%avg = sub <16 x i16> %or, %shift
ret <16 x i16> %avg
}
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