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[AMDGPU] Fix lowering of abs for i16 vectors with more than 2 elements #95413

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Merged
merged 4 commits into from
Jun 14, 2024
Merged

[AMDGPU] Fix lowering of abs for i16 vectors with more than 2 elements #95413

merged 4 commits into from
Jun 14, 2024

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tgymnich
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fixes #94606

Expansion of ABS for i16 vectors with more than 2 elements is currently falling back to scalarization of the vector.
This PR adds a custom lowering for ABS on i16 vectors that splits the vector into multiple <2 x i 16> vectors.

@llvmbot
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llvmbot commented Jun 13, 2024

@llvm/pr-subscribers-backend-amdgpu

Author: Tim Gymnich (tgymnich)

Changes

fixes #94606

Expansion of ABS for i16 vectors with more than 2 elements is currently falling back to scalarization of the vector.
This PR adds a custom lowering for ABS on i16 vectors that splits the vector into multiple &lt;2 x i 16&gt; vectors.

Patch is 50.94 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/95413.diff

2 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+2-1)
  • (added) llvm/test/CodeGen/AMDGPU/abs.ll (+1152)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 81098201e9c0f..c030a9117340a 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -791,7 +791,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
     for (MVT VT : {MVT::v4i16, MVT::v8i16, MVT::v16i16, MVT::v32i16})
       // Split vector operations.
       setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL, ISD::ADD, ISD::SUB,
-                          ISD::MUL, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX,
+                          ISD::MUL, ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX,
                           ISD::UADDSAT, ISD::SADDSAT, ISD::USUBSAT,
                           ISD::SSUBSAT},
                          VT, Custom);
@@ -5804,6 +5804,7 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
     return lowerTRAP(Op, DAG);
   case ISD::DEBUGTRAP:
     return lowerDEBUGTRAP(Op, DAG);
+  case ISD::ABS:
   case ISD::FABS:
   case ISD::FNEG:
   case ISD::FCANONICALIZE:
diff --git a/llvm/test/CodeGen/AMDGPU/abs.ll b/llvm/test/CodeGen/AMDGPU/abs.ll
new file mode 100644
index 0000000000000..fdea3963f3ae6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/abs.ll
@@ -0,0 +1,1152 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx600 < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx700 < %s | FileCheck -check-prefix=GFX7 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx803 < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+
+
+define <4 x i16> @v_abs_v4i16(<4 x i16> %arg) {
+; GFX6-LABEL: v_abs_v4i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX6-NEXT:    v_bfe_i32 v3, v3, 0, 16
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
+; GFX6-NEXT:    v_max_i32_e32 v2, v2, v4
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
+; GFX6-NEXT:    v_max_i32_e32 v3, v3, v4
+; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
+; GFX6-NEXT:    v_max_i32_e32 v0, v0, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
+; GFX6-NEXT:    v_max_i32_e32 v1, v1, v3
+; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT:    v_alignbit_b32 v1, v2, v0, 16
+; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_abs_v4i16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX7-NEXT:    v_bfe_i32 v3, v3, 0, 16
+; GFX7-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
+; GFX7-NEXT:    v_max_i32_e32 v2, v2, v4
+; GFX7-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
+; GFX7-NEXT:    v_max_i32_e32 v3, v3, v4
+; GFX7-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX7-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX7-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
+; GFX7-NEXT:    v_max_i32_e32 v0, v0, v3
+; GFX7-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
+; GFX7-NEXT:    v_max_i32_e32 v1, v1, v3
+; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT:    v_alignbit_b32 v1, v2, v0, 16
+; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_abs_v4i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 16, v1
+; GFX8-NEXT:    v_sub_u16_e32 v3, 0, v2
+; GFX8-NEXT:    v_max_i16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
+; GFX8-NEXT:    v_sub_u16_e32 v4, 0, v3
+; GFX8-NEXT:    v_max_i16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_sub_u16_e32 v4, 0, v1
+; GFX8-NEXT:    v_sub_u16_e32 v5, 0, v0
+; GFX8-NEXT:    v_max_i16_e32 v0, v0, v5
+; GFX8-NEXT:    v_max_i16_e32 v1, v1, v4
+; GFX8-NEXT:    v_or_b32_e32 v0, v0, v3
+; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_abs_v4i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_pk_sub_i16 v2, 0, v0
+; GFX9-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX9-NEXT:    v_pk_sub_i16 v2, 0, v1
+; GFX9-NEXT:    v_pk_max_i16 v1, v1, v2
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_abs_v4i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_pk_sub_i16 v2, 0, v0
+; GFX10-NEXT:    v_pk_sub_i16 v3, 0, v1
+; GFX10-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX10-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_abs_v4i16:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_pk_sub_i16 v2, 0, v0
+; GFX11-NEXT:    v_pk_sub_i16 v3, 0, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX11-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_abs_v4i16:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT:    s_wait_expcnt 0x0
+; GFX12-NEXT:    s_wait_samplecnt 0x0
+; GFX12-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NEXT:    v_pk_sub_i16 v2, 0, v0
+; GFX12-NEXT:    v_pk_sub_i16 v3, 0, v1
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX12-NEXT:    v_pk_max_i16 v1, v1, v3
+; GFX12-NEXT:    s_setpc_b64 s[30:31]
+  %res = call <4 x i16> @llvm.abs.v4i16(<4 x i16> %arg, i1 false)
+  ret <4 x i16> %res
+}
+
+define <8 x i16> @v_abs_v8i16(<8 x i16> %arg) {
+; GFX6-LABEL: v_abs_v8i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v6, v6, 0, 16
+; GFX6-NEXT:    v_bfe_i32 v7, v7, 0, 16
+; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, 0, v6
+; GFX6-NEXT:    v_max_i32_e32 v6, v6, v8
+; GFX6-NEXT:    v_sub_i32_e32 v8, vcc, 0, v7
+; GFX6-NEXT:    v_max_i32_e32 v7, v7, v8
+; GFX6-NEXT:    v_bfe_i32 v4, v4, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX6-NEXT:    v_bfe_i32 v5, v5, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, 0, v4
+; GFX6-NEXT:    v_max_i32_e32 v4, v4, v7
+; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
+; GFX6-NEXT:    v_max_i32_e32 v5, v5, v7
+; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX6-NEXT:    v_bfe_i32 v3, v3, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, 0, v2
+; GFX6-NEXT:    v_max_i32_e32 v2, v2, v5
+; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, 0, v3
+; GFX6-NEXT:    v_max_i32_e32 v3, v3, v5
+; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
+; GFX6-NEXT:    v_max_i32_e32 v0, v0, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
+; GFX6-NEXT:    v_max_i32_e32 v1, v1, v3
+; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT:    v_alignbit_b32 v1, v2, v0, 16
+; GFX6-NEXT:    v_alignbit_b32 v5, v6, v4, 16
+; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX6-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_abs_v8i16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_bfe_i32 v6, v6, 0, 16
+; GFX7-NEXT:    v_bfe_i32 v7, v7, 0, 16
+; GFX7-NEXT:    v_sub_i32_e32 v8, vcc, 0, v6
+; GFX7-NEXT:    v_max_i32_e32 v6, v6, v8
+; GFX7-NEXT:    v_sub_i32_e32 v8, vcc, 0, v7
+; GFX7-NEXT:    v_max_i32_e32 v7, v7, v8
+; GFX7-NEXT:    v_bfe_i32 v4, v4, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX7-NEXT:    v_bfe_i32 v5, v5, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX7-NEXT:    v_sub_i32_e32 v7, vcc, 0, v4
+; GFX7-NEXT:    v_max_i32_e32 v4, v4, v7
+; GFX7-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
+; GFX7-NEXT:    v_max_i32_e32 v5, v5, v7
+; GFX7-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX7-NEXT:    v_bfe_i32 v3, v3, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX7-NEXT:    v_sub_i32_e32 v5, vcc, 0, v2
+; GFX7-NEXT:    v_max_i32_e32 v2, v2, v5
+; GFX7-NEXT:    v_sub_i32_e32 v5, vcc, 0, v3
+; GFX7-NEXT:    v_max_i32_e32 v3, v3, v5
+; GFX7-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX7-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX7-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
+; GFX7-NEXT:    v_max_i32_e32 v0, v0, v3
+; GFX7-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
+; GFX7-NEXT:    v_max_i32_e32 v1, v1, v3
+; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT:    v_alignbit_b32 v1, v2, v0, 16
+; GFX7-NEXT:    v_alignbit_b32 v5, v6, v4, 16
+; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX7-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_abs_v8i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v3
+; GFX8-NEXT:    v_sub_u16_e32 v5, 0, v4
+; GFX8-NEXT:    v_max_i16_sdwa v4, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 16, v2
+; GFX8-NEXT:    v_sub_u16_e32 v6, 0, v5
+; GFX8-NEXT:    v_max_i16_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
+; GFX8-NEXT:    v_sub_u16_e32 v7, 0, v6
+; GFX8-NEXT:    v_max_i16_sdwa v6, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 16, v0
+; GFX8-NEXT:    v_sub_u16_e32 v8, 0, v7
+; GFX8-NEXT:    v_max_i16_sdwa v7, v7, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_sub_u16_e32 v8, 0, v3
+; GFX8-NEXT:    v_sub_u16_e32 v9, 0, v2
+; GFX8-NEXT:    v_sub_u16_e32 v10, 0, v1
+; GFX8-NEXT:    v_sub_u16_e32 v11, 0, v0
+; GFX8-NEXT:    v_max_i16_e32 v0, v0, v11
+; GFX8-NEXT:    v_max_i16_e32 v1, v1, v10
+; GFX8-NEXT:    v_max_i16_e32 v2, v2, v9
+; GFX8-NEXT:    v_max_i16_e32 v3, v3, v8
+; GFX8-NEXT:    v_or_b32_e32 v0, v0, v7
+; GFX8-NEXT:    v_or_b32_e32 v1, v1, v6
+; GFX8-NEXT:    v_or_b32_e32 v2, v2, v5
+; GFX8-NEXT:    v_or_b32_e32 v3, v3, v4
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_abs_v8i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_pk_sub_i16 v4, 0, v0
+; GFX9-NEXT:    v_pk_max_i16 v0, v0, v4
+; GFX9-NEXT:    v_pk_sub_i16 v4, 0, v1
+; GFX9-NEXT:    v_pk_max_i16 v1, v1, v4
+; GFX9-NEXT:    v_pk_sub_i16 v4, 0, v2
+; GFX9-NEXT:    v_pk_max_i16 v2, v2, v4
+; GFX9-NEXT:    v_pk_sub_i16 v4, 0, v3
+; GFX9-NEXT:    v_pk_max_i16 v3, v3, v4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_abs_v8i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_pk_sub_i16 v4, 0, v0
+; GFX10-NEXT:    v_pk_sub_i16 v5, 0, v1
+; GFX10-NEXT:    v_pk_sub_i16 v6, 0, v2
+; GFX10-NEXT:    v_pk_sub_i16 v7, 0, v3
+; GFX10-NEXT:    v_pk_max_i16 v0, v0, v4
+; GFX10-NEXT:    v_pk_max_i16 v1, v1, v5
+; GFX10-NEXT:    v_pk_max_i16 v2, v2, v6
+; GFX10-NEXT:    v_pk_max_i16 v3, v3, v7
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_abs_v8i16:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_pk_sub_i16 v4, 0, v0
+; GFX11-NEXT:    v_pk_sub_i16 v5, 0, v1
+; GFX11-NEXT:    v_pk_sub_i16 v6, 0, v2
+; GFX11-NEXT:    v_pk_sub_i16 v7, 0, v3
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_pk_max_i16 v0, v0, v4
+; GFX11-NEXT:    v_pk_max_i16 v1, v1, v5
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_pk_max_i16 v2, v2, v6
+; GFX11-NEXT:    v_pk_max_i16 v3, v3, v7
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: v_abs_v8i16:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT:    s_wait_expcnt 0x0
+; GFX12-NEXT:    s_wait_samplecnt 0x0
+; GFX12-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NEXT:    v_pk_sub_i16 v4, 0, v0
+; GFX12-NEXT:    v_pk_sub_i16 v5, 0, v1
+; GFX12-NEXT:    v_pk_sub_i16 v6, 0, v2
+; GFX12-NEXT:    v_pk_sub_i16 v7, 0, v3
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-NEXT:    v_pk_max_i16 v0, v0, v4
+; GFX12-NEXT:    v_pk_max_i16 v1, v1, v5
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-NEXT:    v_pk_max_i16 v2, v2, v6
+; GFX12-NEXT:    v_pk_max_i16 v3, v3, v7
+; GFX12-NEXT:    s_setpc_b64 s[30:31]
+  %res = call <8 x i16> @llvm.abs.v8i16(<8 x i16> %arg, i1 false)
+  ret <8 x i16> %res
+}
+
+
+define <16 x i16> @v_abs_v16i16(<16 x i16> %arg) {
+; GFX6-LABEL: v_abs_v16i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v14, v14, 0, 16
+; GFX6-NEXT:    v_bfe_i32 v15, v15, 0, 16
+; GFX6-NEXT:    v_sub_i32_e32 v16, vcc, 0, v14
+; GFX6-NEXT:    v_max_i32_e32 v14, v14, v16
+; GFX6-NEXT:    v_sub_i32_e32 v16, vcc, 0, v15
+; GFX6-NEXT:    v_max_i32_e32 v15, v15, v16
+; GFX6-NEXT:    v_bfe_i32 v12, v12, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX6-NEXT:    v_bfe_i32 v13, v13, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v14, v14, v15
+; GFX6-NEXT:    v_sub_i32_e32 v15, vcc, 0, v12
+; GFX6-NEXT:    v_max_i32_e32 v12, v12, v15
+; GFX6-NEXT:    v_sub_i32_e32 v15, vcc, 0, v13
+; GFX6-NEXT:    v_max_i32_e32 v13, v13, v15
+; GFX6-NEXT:    v_bfe_i32 v10, v10, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX6-NEXT:    v_bfe_i32 v11, v11, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX6-NEXT:    v_sub_i32_e32 v13, vcc, 0, v10
+; GFX6-NEXT:    v_max_i32_e32 v10, v10, v13
+; GFX6-NEXT:    v_sub_i32_e32 v13, vcc, 0, v11
+; GFX6-NEXT:    v_max_i32_e32 v11, v11, v13
+; GFX6-NEXT:    v_bfe_i32 v8, v8, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX6-NEXT:    v_bfe_i32 v9, v9, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX6-NEXT:    v_sub_i32_e32 v11, vcc, 0, v8
+; GFX6-NEXT:    v_max_i32_e32 v8, v8, v11
+; GFX6-NEXT:    v_sub_i32_e32 v11, vcc, 0, v9
+; GFX6-NEXT:    v_max_i32_e32 v9, v9, v11
+; GFX6-NEXT:    v_bfe_i32 v6, v6, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX6-NEXT:    v_bfe_i32 v7, v7, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, 0, v6
+; GFX6-NEXT:    v_max_i32_e32 v6, v6, v9
+; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, 0, v7
+; GFX6-NEXT:    v_max_i32_e32 v7, v7, v9
+; GFX6-NEXT:    v_bfe_i32 v4, v4, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX6-NEXT:    v_bfe_i32 v5, v5, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, 0, v4
+; GFX6-NEXT:    v_max_i32_e32 v4, v4, v7
+; GFX6-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
+; GFX6-NEXT:    v_max_i32_e32 v5, v5, v7
+; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX6-NEXT:    v_bfe_i32 v3, v3, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, 0, v2
+; GFX6-NEXT:    v_max_i32_e32 v2, v2, v5
+; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, 0, v3
+; GFX6-NEXT:    v_max_i32_e32 v3, v3, v5
+; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
+; GFX6-NEXT:    v_max_i32_e32 v0, v0, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
+; GFX6-NEXT:    v_max_i32_e32 v1, v1, v3
+; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT:    v_alignbit_b32 v1, v2, v0, 16
+; GFX6-NEXT:    v_alignbit_b32 v5, v6, v4, 16
+; GFX6-NEXT:    v_alignbit_b32 v9, v10, v8, 16
+; GFX6-NEXT:    v_alignbit_b32 v13, v14, v12, 16
+; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX6-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
+; GFX6-NEXT:    v_lshrrev_b32_e32 v11, 16, v10
+; GFX6-NEXT:    v_lshrrev_b32_e32 v15, 16, v14
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_abs_v16i16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_bfe_i32 v14, v14, 0, 16
+; GFX7-NEXT:    v_bfe_i32 v15, v15, 0, 16
+; GFX7-NEXT:    v_sub_i32_e32 v16, vcc, 0, v14
+; GFX7-NEXT:    v_max_i32_e32 v14, v14, v16
+; GFX7-NEXT:    v_sub_i32_e32 v16, vcc, 0, v15
+; GFX7-NEXT:    v_max_i32_e32 v15, v15, v16
+; GFX7-NEXT:    v_bfe_i32 v12, v12, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v15, 16, v15
+; GFX7-NEXT:    v_bfe_i32 v13, v13, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v14, v14, v15
+; GFX7-NEXT:    v_sub_i32_e32 v15, vcc, 0, v12
+; GFX7-NEXT:    v_max_i32_e32 v12, v12, v15
+; GFX7-NEXT:    v_sub_i32_e32 v15, vcc, 0, v13
+; GFX7-NEXT:    v_max_i32_e32 v13, v13, v15
+; GFX7-NEXT:    v_bfe_i32 v10, v10, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v13, 16, v13
+; GFX7-NEXT:    v_bfe_i32 v11, v11, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v12, v12, v13
+; GFX7-NEXT:    v_sub_i32_e32 v13, vcc, 0, v10
+; GFX7-NEXT:    v_max_i32_e32 v10, v10, v13
+; GFX7-NEXT:    v_sub_i32_e32 v13, vcc, 0, v11
+; GFX7-NEXT:    v_max_i32_e32 v11, v11, v13
+; GFX7-NEXT:    v_bfe_i32 v8, v8, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v11, 16, v11
+; GFX7-NEXT:    v_bfe_i32 v9, v9, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX7-NEXT:    v_sub_i32_e32 v11, vcc, 0, v8
+; GFX7-NEXT:    v_max_i32_e32 v8, v8, v11
+; GFX7-NEXT:    v_sub_i32_e32 v11, vcc, 0, v9
+; GFX7-NEXT:    v_max_i32_e32 v9, v9, v11
+; GFX7-NEXT:    v_bfe_i32 v6, v6, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v9, 16, v9
+; GFX7-NEXT:    v_bfe_i32 v7, v7, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX7-NEXT:    v_sub_i32_e32 v9, vcc, 0, v6
+; GFX7-NEXT:    v_max_i32_e32 v6, v6, v9
+; GFX7-NEXT:    v_sub_i32_e32 v9, vcc, 0, v7
+; GFX7-NEXT:    v_max_i32_e32 v7, v7, v9
+; GFX7-NEXT:    v_bfe_i32 v4, v4, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v7, 16, v7
+; GFX7-NEXT:    v_bfe_i32 v5, v5, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX7-NEXT:    v_sub_i32_e32 v7, vcc, 0, v4
+; GFX7-NEXT:    v_max_i32_e32 v4, v4, v7
+; GFX7-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
+; GFX7-NEXT:    v_max_i32_e32 v5, v5, v7
+; GFX7-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX7-NEXT:    v_bfe_i32 v3, v3, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX7-NEXT:    v_sub_i32_e32 v5, vcc, 0, v2
+; GFX7-NEXT:    v_max_i32_e32 v2, v2, v5
+; GFX7-NEXT:    v_sub_i32_e32 v5, vcc, 0, v3
+; GFX7-NEXT:    v_max_i32_e32 v3, v3, v5
+; GFX7-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX7-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
+; GFX7-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX7-NEXT:    v_or_b32_e32 v2, v2, v3
+; GFX7-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
+; GFX7-NEXT:    v_max_i32_e32 v0, v0, v3
+; GFX7-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
+; GFX7-NEXT:    v_max_i32_e32 v1, v1, v3
+; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT:    v_alignbit_b32 v1, v2, v0, 16
+; GFX7-NEXT:    v_alignbit_b32 v5, v6, v4, 16
+; GFX7-NEXT:    v_alignbit_b32 v9, v10, v8, 16
+; GFX7-NEXT:    v_alignbit_b32 v13, v14, v12, 16
+; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
+; GFX7-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
+; GFX7-NEXT:    v_lshrrev_b32_e32 v11, 16, v10
+; GFX7-NEXT:    v_lshrrev_b32_e3...
[truncated]

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✅ With the latest revision this PR passed the C/C++ code formatter.

arsenm
arsenm reviewed Jun 13, 2024
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llvm/test/CodeGen/AMDGPU/abs.ll Outdated
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s

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We apparently don't have existing tests for this, so you should also test the scalar, 2 and 3 element cases, and maybe 6.

Also we should have the 32/64cases, but I guess you can just add an i16 suffix to the test and leave those for later. Also would be nice to cover the basic SALU cases

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done

@tgymnich tgymnich force-pushed the AMDGPU-v_abs_v4i16 branch from af0ab22 to f21de54 Compare June 13, 2024 20:45
@tgymnich tgymnich requested a review from arsenm June 13, 2024 20:46
@arsenm arsenm merged commit 7091dd2 into llvm:main Jun 14, 2024
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nico commented Jun 14, 2024

Looks like this breaks tests: http://45.33.8.238/linux/140660/step_11.txt

Please take a look and revert for now if it takes a while to fix.

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#95620

@tgymnich tgymnich deleted the AMDGPU-v_abs_v4i16 branch June 15, 2024 16:44
@jpienaar jpienaar mentioned this pull request Jun 17, 2024
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AMDGPU lowering of abs is bad for i16 vectors with more than 2 elements
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@tgymnich @llvmbot @nico @jrbyrnes @arsenm