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[AArch64] LowerAVG - fallback to default expansion #95416

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Merged
merged 1 commit into from
Jun 14, 2024
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[AArch64] LowerAVG - fallback to default expansion #95416

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46 changes: 2 additions & 44 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14995,55 +14995,13 @@ AArch64TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
return SDValue();
}

// When x and y are extended, lower:
// avgfloor(x, y) -> (x + y) >> 1
// avgceil(x, y) -> (x + y + 1) >> 1

// Otherwise, lower to:
// avgfloor(x, y) -> (x >> 1) + (y >> 1) + (x & y & 1)
// avgceil(x, y) -> (x >> 1) + (y >> 1) + ((x || y) & 1)
SDValue AArch64TargetLowering::LowerAVG(SDValue Op, SelectionDAG &DAG,
unsigned NewOp) const {
if (Subtarget->hasSVE2())
return LowerToPredicatedOp(Op, DAG, NewOp);

SDLoc dl(Op);
SDValue OpA = Op->getOperand(0);
SDValue OpB = Op->getOperand(1);
EVT VT = Op.getValueType();
bool IsCeil =
(Op->getOpcode() == ISD::AVGCEILS || Op->getOpcode() == ISD::AVGCEILU);
bool IsSigned =
(Op->getOpcode() == ISD::AVGFLOORS || Op->getOpcode() == ISD::AVGCEILS);
unsigned ShiftOpc = IsSigned ? ISD::SRA : ISD::SRL;

assert(VT.isScalableVector() && "Only expect to lower scalable vector op!");

auto IsZeroExtended = [&DAG](SDValue &Node) {
KnownBits Known = DAG.computeKnownBits(Node, 0);
return Known.Zero.isSignBitSet();
};

auto IsSignExtended = [&DAG](SDValue &Node) {
return (DAG.ComputeNumSignBits(Node, 0) > 1);
};

SDValue ConstantOne = DAG.getConstant(1, dl, VT);
if ((!IsSigned && IsZeroExtended(OpA) && IsZeroExtended(OpB)) ||
(IsSigned && IsSignExtended(OpA) && IsSignExtended(OpB))) {
SDValue Add = DAG.getNode(ISD::ADD, dl, VT, OpA, OpB);
if (IsCeil)
Add = DAG.getNode(ISD::ADD, dl, VT, Add, ConstantOne);
return DAG.getNode(ShiftOpc, dl, VT, Add, ConstantOne);
}

SDValue ShiftOpA = DAG.getNode(ShiftOpc, dl, VT, OpA, ConstantOne);
SDValue ShiftOpB = DAG.getNode(ShiftOpc, dl, VT, OpB, ConstantOne);

SDValue tmp = DAG.getNode(IsCeil ? ISD::OR : ISD::AND, dl, VT, OpA, OpB);
tmp = DAG.getNode(ISD::AND, dl, VT, tmp, ConstantOne);
SDValue Add = DAG.getNode(ISD::ADD, dl, VT, ShiftOpA, ShiftOpB);
return DAG.getNode(ISD::ADD, dl, VT, Add, tmp);
// Default to expand.
return SDValue();
}

SDValue AArch64TargetLowering::LowerVSCALE(SDValue Op,
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