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[AArch64][GlobalISel] Add fp128 and i128 fptosi/fptoui handling. #95528

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Jun 21, 2024
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10 changes: 4 additions & 6 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1123,15 +1123,13 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
case TargetOpcode::G_FPTOSI:
case TargetOpcode::G_FPTOUI: {
// FIXME: Support other types
unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
Type *FromTy =
getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(1).getReg()));
unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
if ((ToSize != 32 && ToSize != 64 && ToSize != 128) || !FromTy)
return UnableToLegalize;
LegalizeResult Status = conversionLibcall(
MI, MIRBuilder,
ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
LocObserver);
MI, MIRBuilder, Type::getIntNTy(Ctx, ToSize), FromTy, LocObserver);
if (Status != Legalized)
return Status;
break;
Expand Down
38 changes: 28 additions & 10 deletions llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -661,34 +661,52 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)

// Conversions
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
.legalForCartesianProduct({s32, s64, v2s64, v4s32, v2s32})
.legalFor({{s32, s32},
{s64, s32},
{s32, s64},
{s64, s64},
{v2s64, v2s64},
{v4s32, v4s32},
{v2s32, v2s32}})
.legalIf([=](const LegalityQuery &Query) {
return HasFP16 &&
(Query.Types[1] == s16 || Query.Types[1] == v4s16 ||
Query.Types[1] == v8s16) &&
(Query.Types[0] == s32 || Query.Types[0] == s64 ||
Query.Types[0] == v4s16 || Query.Types[0] == v8s16);
})
.widenScalarToNextPow2(0)
.clampScalar(0, s32, s64)
.widenScalarToNextPow2(1)
.clampScalarOrElt(1, MinFPScalar, s64)
.scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
.scalarizeIf(scalarOrEltWiderThan(1, 64), 1)
// The range of a fp16 value fits into an i17, so we can lower the width
// to i64.
.narrowScalarIf(
[=](const LegalityQuery &Query) {
return Query.Types[1] == s16 && Query.Types[0].getSizeInBits() > 64;
},
changeTo(0, s64))
.moreElementsToNextPow2(0)
.widenScalarOrEltToNextPow2OrMinSize(0)
.minScalar(0, s32)
.widenScalarOrEltToNextPow2OrMinSize(1, /*MinSize=*/HasFP16 ? 16 : 32)
.widenScalarIf(
[=](const LegalityQuery &Query) {
return Query.Types[0].getScalarSizeInBits() >
Query.Types[1].getScalarSizeInBits();
return Query.Types[0].getScalarSizeInBits() <= 64 &&
Query.Types[0].getScalarSizeInBits() >
Query.Types[1].getScalarSizeInBits();
},
LegalizeMutations::changeElementSizeTo(1, 0))
.widenScalarIf(
[=](const LegalityQuery &Query) {
return Query.Types[0].getScalarSizeInBits() <
Query.Types[1].getScalarSizeInBits();
return Query.Types[1].getScalarSizeInBits() <= 64 &&
Query.Types[0].getScalarSizeInBits() <
Query.Types[1].getScalarSizeInBits();
},
LegalizeMutations::changeElementSizeTo(0, 1))
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
.clampMaxNumElements(0, s64, 2);
.clampMaxNumElements(0, s64, 2)
.libcallFor(
{{s32, s128}, {s64, s128}, {s128, s128}, {s128, s32}, {s128, s64}});

getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
.legalForCartesianProduct({s32, s64, v2s64, v4s32, v2s32})
Expand Down

This file was deleted.

76 changes: 0 additions & 76 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
Original file line number Diff line number Diff line change
Expand Up @@ -711,79 +711,3 @@ body: |
%1:fpr(<2 x s32>) = G_UITOFP %0
$d0 = COPY %1(<2 x s32>)
...

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Why remove these tests?

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They were testing a v2s32->v2s64 G_FPTOSI, which are nowadays no longer legal. We split into two operations earlier during legalization. It shouldn't alter the end result, but feels a bit cleaner.

---
name: fptosi_v2s64_v2s32
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $d0

; CHECK-LABEL: name: fptosi_v2s64_v2s32
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[FCVTLv2i32_]]
; CHECK: $q0 = COPY [[FCVTZSv2f64_]]
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s64>) = G_FPTOSI %0
$q0 = COPY %1(<2 x s64>)
...

---
name: fptoui_v2s64_v2s32
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $d0

; CHECK-LABEL: name: fptoui_v2s64_v2s32
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[FCVTLv2i32_]]
; CHECK: $q0 = COPY [[FCVTZUv2f64_]]
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s64>) = G_FPTOUI %0
$q0 = COPY %1(<2 x s64>)
...

---
name: fptosi_v2s32_v2s64
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $q0

; CHECK-LABEL: name: fptosi_v2s32_v2s64
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[COPY]]
; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[FCVTZSv2f64_]]
; CHECK: $d0 = COPY [[XTNv2i32_]]
%0:fpr(<2 x s64>) = COPY $q0
%1:fpr(<2 x s32>) = G_FPTOSI %0
$d0 = COPY %1(<2 x s32>)
...

---
name: fptoui_v2s32_v2s64
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: $q0

; CHECK-LABEL: name: fptoui_v2s32_v2s64
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[COPY]]
; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[FCVTZUv2f64_]]
; CHECK: $d0 = COPY [[XTNv2i32_]]
%0:fpr(<2 x s64>) = COPY $q0
%1:fpr(<2 x s32>) = G_FPTOUI %0
$d0 = COPY %1(<2 x s32>)
...
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