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Jun 19, 2024
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[mlir][ArmSVE] Add arm_sve.psel operation #95764

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47771eb
[mlir][ArmSVE] Add `arm_sve.psel` operation
MacDue Jun 17, 2024
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MacDue Jun 17, 2024
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MacDue Jun 17, 2024
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55 changes: 53 additions & 2 deletions mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
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Original file line number Diff line number Diff line change
Expand Up @@ -37,10 +37,16 @@ def ArmSVE_Dialect : Dialect {
//===----------------------------------------------------------------------===//

def SVBool : ScalableVectorOfRankAndLengthAndType<
[1], [16], [I1]>;
[1], [16], [I1]>
{
let summary = "vector<[16]xi1>";
}

def SVEPredicate : ScalableVectorOfRankAndLengthAndType<
[1], [16, 8, 4, 2, 1], [I1]>;
[1], [16, 8, 4, 2, 1], [I1]>
{
let summary = "vector<[1]xi1>, vector<[2]xi1>, vector<[4]xi1>, vector<[8]xi1>, or vector<[16]xi1>";
}

// Generalizations of SVBool and SVEPredicate to ranks >= 1.
// These are masks with a single trailing scalable dimension.
Expand Down Expand Up @@ -442,6 +448,43 @@ def ZipX4Op : ArmSVE_Op<"zip.x4", [
}];
}

def PselOp : ArmSVE_Op<"psel", [
Pure,
AllTypesMatch<["p1", "result"]>,
]> {
let summary = "Predicate select";

let description = [{
This operation returns the input predicate `p1` or an all-false predicate
based on the bit at `p2[index]`. Informally, the semantics are:
```
if p2[index % num_elements(p2)] == 1:
return p1 : type(p1)
return all-false : type(p1)
```

Example:
```mlir
// Note: p1 and p2 can have different sizes.
%pd = arm_sve.psel %p1, %p2[%index] : vector<[4]xi1>, vector<[8]xi1>
```

Note: This requires SME or SVE2.1 (`+sme` or `+sve2p1` in LLVM target features).
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Suggested change
Note: This requires SME or SVE2.1 (`+sme` or `+sve2p1` in LLVM target features).
Note: This requires SME or SVE2.1 (`+sme` or `+sve2p1` in LLVM target features when lowering to assembly and/or machine code).

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This would be inconsistent with other ArmSVE ops and is not really true. Feature flags are used much earlier to check things within IREE, for example.

}];

let arguments = (ins SVEPredicate:$p1, SVEPredicate:$p2, Index:$index);
let results = (outs SVEPredicate:$result);

let builders = [
OpBuilder<(ins "Value":$p1, "Value":$p2, "Value":$index), [{
build($_builder, $_state, p1.getType(), p1, p2, index);
}]>];

let assemblyFormat = [{
$p1 `,` $p2 `[` $index `]` attr-dict `:` type($p1) `,` type($p2)
}];
}

def ScalableMaskedAddIOp : ScalableMaskedIOp<"masked.addi", "addition",
[Commutative]>;

Expand Down Expand Up @@ -552,6 +595,14 @@ def ZipX4IntrOp : ArmSVE_IntrOp<"zip.x4",
Arg<AnyScalableVector, "v3">:$v3,
Arg<AnyScalableVector, "v3">:$v4)>;

// Note: This intrinsic requires SME or SVE2.1.
def PselIntrOp : ArmSVE_IntrOp<"psel",
/*traits=*/[Pure, TypeIs<"res", SVBool>],
/*overloadedOperands=*/[1]>,
Arguments<(ins Arg<SVBool, "p1">:$p1,
Arg<SVEPredicate, "p2">:$p2,
Arg<I32, "index">:$index)>;

def WhileLTIntrOp :
ArmSVE_IntrOp<"whilelt",
[TypeIs<"res", SVEPredicate>, Pure],
Expand Down
26 changes: 25 additions & 1 deletion mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp
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Expand Up @@ -140,6 +140,28 @@ using ConvertFromSvboolOpLowering =
using ZipX2OpLowering = OneToOneConvertToLLVMPattern<ZipX2Op, ZipX2IntrOp>;
using ZipX4OpLowering = OneToOneConvertToLLVMPattern<ZipX4Op, ZipX4IntrOp>;

/// Lower `arm_sve.psel` to LLVM intrinsics. This is almost a 1-to-1 conversion
/// but first input (P1) and result predicates need conversion to/from svbool.
struct PselOpLowering : public ConvertOpToLLVMPattern<PselOp> {
using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern;

LogicalResult
matchAndRewrite(PselOp pselOp, PselOp::Adaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
auto svboolType = VectorType::get(16, rewriter.getI1Type(), true);
auto loc = pselOp.getLoc();
auto svboolP1 = rewriter.create<ConvertToSvboolIntrOp>(loc, svboolType,
adaptor.getP1());
auto indexI32 = rewriter.create<arith::IndexCastOp>(
loc, rewriter.getI32Type(), pselOp.getIndex());
auto pselIntr = rewriter.create<PselIntrOp>(loc, svboolType, svboolP1,
pselOp.getP2(), indexI32);
rewriter.replaceOpWithNewOp<ConvertFromSvboolIntrOp>(
pselOp, adaptor.getP1().getType(), pselIntr);
return success();
}
};

/// Converts `vector.create_mask` ops that match the size of an SVE predicate
/// to the `whilelt` intrinsic. This produces more canonical codegen than the
/// generic LLVM lowering, see https://github.com/llvm/llvm-project/issues/81840
Expand Down Expand Up @@ -202,7 +224,8 @@ void mlir::populateArmSVELegalizeForLLVMExportPatterns(
ConvertToSvboolOpLowering,
ConvertFromSvboolOpLowering,
ZipX2OpLowering,
ZipX4OpLowering>(converter);
ZipX4OpLowering,
PselOpLowering>(converter);
// Add vector.create_mask conversion with a high benefit as it produces much
// nicer code than the generic lowering.
patterns.add<CreateMaskOpLowering>(converter, /*benefit=*/4096);
Expand All @@ -229,6 +252,7 @@ void mlir::configureArmSVELegalizeForExportTarget(
ConvertFromSvboolIntrOp,
ZipX2IntrOp,
ZipX4IntrOp,
PselIntrOp,
WhileLTIntrOp>();
target.addIllegalOp<SdotOp,
SmmlaOp,
Expand Down
8 changes: 8 additions & 0 deletions mlir/test/Dialect/ArmSVE/invalid.mlir
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Expand Up @@ -64,3 +64,11 @@ func.func @arm_sve_zip_x4_bad_vector_type(%a : vector<[5]xf64>) {
arm_sve.zip.x4 %a, %a, %a, %a : vector<[5]xf64>
return
}

// -----

func.func @arm_sve_psel_bad_vector_type(%a : vector<[7]xi1>, %index: index) {
// expected-error@+1 {{op operand #0 must be vector<[1]xi1>, vector<[2]xi1>, vector<[4]xi1>, vector<[8]xi1>, or vector<[16]xi1>, but got 'vector<[7]xi1>'}}
arm_sve.psel %a, %a[%index] : vector<[7]xi1>, vector<[7]xi1>
return
}
32 changes: 32 additions & 0 deletions mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir
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Expand Up @@ -239,3 +239,35 @@ func.func @arm_sve_unsupported_create_masks(%index: index) -> (vector<[1]xi1>, v
%2 = vector.create_mask %index : vector<[32]xi1>
return %0, %1, %2 : vector<[1]xi1>, vector<[7]xi1>, vector<[32]xi1>
}

// -----

// CHECK-LABEL: @arm_sve_psel_matching_predicate_types(
// CHECK-SAME: %[[P0:[a-z0-9]+]]: vector<[4]xi1>,
// CHECK-SAME: %[[P1:[a-z0-9]+]]: vector<[4]xi1>,
// CHECK-SAME: %[[INDEX:[a-z0-9]+]]: i64
func.func @arm_sve_psel_matching_predicate_types(%p0: vector<[4]xi1>, %p1: vector<[4]xi1>, %index: index) -> vector<[4]xi1>
{
// CHECK-DAG: %[[INDEX_I32:.*]] = llvm.trunc %[[INDEX]] : i64 to i32
// CHECK-DAG: %[[P0_IN:.*]] = "arm_sve.intr.convert.to.svbool"(%[[P0]]) : (vector<[4]xi1>) -> vector<[16]xi1>
// CHECK-NEXT: %[[PSEL:.*]] = "arm_sve.intr.psel"(%[[P0_IN]], %[[P1]], %[[INDEX_I32]]) : (vector<[16]xi1>, vector<[4]xi1>, i32) -> vector<[16]xi1>
// CHECK-NEXT: %[[RES:.*]] = "arm_sve.intr.convert.from.svbool"(%[[PSEL]]) : (vector<[16]xi1>) -> vector<[4]xi1>
%0 = arm_sve.psel %p0, %p1[%index] : vector<[4]xi1>, vector<[4]xi1>
return %0 : vector<[4]xi1>
}

// -----

// CHECK-LABEL: @arm_sve_psel_mixed_predicate_types(
// CHECK-SAME: %[[P0:[a-z0-9]+]]: vector<[8]xi1>,
// CHECK-SAME: %[[P1:[a-z0-9]+]]: vector<[16]xi1>,
// CHECK-SAME: %[[INDEX:[a-z0-9]+]]: i64
func.func @arm_sve_psel_mixed_predicate_types(%p0: vector<[8]xi1>, %p1: vector<[16]xi1>, %index: index) -> vector<[8]xi1>
{
// CHECK-DAG: %[[INDEX_I32:.*]] = llvm.trunc %[[INDEX]] : i64 to i32
// CHECK-DAG: %[[P0_IN:.*]] = "arm_sve.intr.convert.to.svbool"(%[[P0]]) : (vector<[8]xi1>) -> vector<[16]xi1>
// CHECK-NEXT: %[[PSEL:.*]] = "arm_sve.intr.psel"(%[[P0_IN]], %[[P1]], %[[INDEX_I32]]) : (vector<[16]xi1>, vector<[16]xi1>, i32) -> vector<[16]xi1>
// CHECK-NEXT: %[[RES:.*]] = "arm_sve.intr.convert.from.svbool"(%[[PSEL]]) : (vector<[16]xi1>) -> vector<[8]xi1>
%0 = arm_sve.psel %p0, %p1[%index] : vector<[8]xi1>, vector<[16]xi1>
return %0 : vector<[8]xi1>
}
29 changes: 29 additions & 0 deletions mlir/test/Dialect/ArmSVE/roundtrip.mlir
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Expand Up @@ -225,3 +225,32 @@ func.func @arm_sve_zip_x4(
%a8, %b8, %c8, %d8 = arm_sve.zip.x4 %v8, %v8, %v8, %v8 : vector<[16]xi8>
return
}

// -----

func.func @arm_sve_psel(
%p0: vector<[2]xi1>,
%p1: vector<[4]xi1>,
%p2: vector<[8]xi1>,
%p3: vector<[16]xi1>,
%index: index
) {
// CHECK: arm_sve.psel %{{.*}}, %{{.*}}[%{{.*}}] : vector<[2]xi1>, vector<[2]xi1>
%0 = arm_sve.psel %p0, %p0[%index] : vector<[2]xi1>, vector<[2]xi1>
// CHECK: arm_sve.psel %{{.*}}, %{{.*}}[%{{.*}}] : vector<[4]xi1>, vector<[4]xi1>
%1 = arm_sve.psel %p1, %p1[%index] : vector<[4]xi1>, vector<[4]xi1>
// CHECK: arm_sve.psel %{{.*}}, %{{.*}}[%{{.*}}] : vector<[8]xi1>, vector<[8]xi1>
%2 = arm_sve.psel %p2, %p2[%index] : vector<[8]xi1>, vector<[8]xi1>
// CHECK: arm_sve.psel %{{.*}}, %{{.*}}[%{{.*}}] : vector<[16]xi1>, vector<[16]xi1>
%3 = arm_sve.psel %p3, %p3[%index] : vector<[16]xi1>, vector<[16]xi1>
/// Some mixed predicate type examples:
// CHECK: arm_sve.psel %{{.*}}, %{{.*}}[%{{.*}}] : vector<[2]xi1>, vector<[4]xi1>
%4 = arm_sve.psel %p0, %p1[%index] : vector<[2]xi1>, vector<[4]xi1>
// CHECK: arm_sve.psel %{{.*}}, %{{.*}}[%{{.*}}] : vector<[4]xi1>, vector<[8]xi1>
%5 = arm_sve.psel %p1, %p2[%index] : vector<[4]xi1>, vector<[8]xi1>
// CHECK: arm_sve.psel %{{.*}}, %{{.*}}[%{{.*}}] : vector<[8]xi1>, vector<[16]xi1>
%6 = arm_sve.psel %p2, %p3[%index] : vector<[8]xi1>, vector<[16]xi1>
// CHECK: arm_sve.psel %{{.*}}, %{{.*}}[%{{.*}}] : vector<[16]xi1>, vector<[2]xi1>
%7 = arm_sve.psel %p3, %p0[%index] : vector<[16]xi1>, vector<[2]xi1>
return
}
19 changes: 19 additions & 0 deletions mlir/test/Target/LLVMIR/arm-sve.mlir
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Expand Up @@ -371,3 +371,22 @@ llvm.func @arm_sve_whilelt(%base: i64, %n: i64) {
%4 = "arm_sve.intr.whilelt"(%base, %n) : (i64, i64) -> vector<[16]xi1>
llvm.return
}

// CHECK-LABEL: arm_sve_psel(
// CHECK-SAME: <vscale x 16 x i1> %[[PN:[0-9]+]],
// CHECK-SAME: <vscale x 2 x i1> %[[P1:[0-9]+]],
// CHECK-SAME: <vscale x 4 x i1> %[[P2:[0-9]+]],
// CHECK-SAME: <vscale x 8 x i1> %[[P3:[0-9]+]],
// CHECK-SAME: <vscale x 16 x i1> %[[P4:[0-9]+]],
// CHECK-SAME: i32 %[[INDEX:[0-9]+]])
llvm.func @arm_sve_psel(%pn: vector<[16]xi1>, %p1: vector<[2]xi1>, %p2: vector<[4]xi1>, %p3: vector<[8]xi1>, %p4: vector<[16]xi1>, %index: i32) {
// CHECK: call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> %[[PN]], <vscale x 2 x i1> %[[P1]], i32 %[[INDEX]])
"arm_sve.intr.psel"(%pn, %p1, %index) : (vector<[16]xi1>, vector<[2]xi1>, i32) -> vector<[16]xi1>
// CHECK: call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> %[[PN]], <vscale x 4 x i1> %[[P2]], i32 %[[INDEX]])
"arm_sve.intr.psel"(%pn, %p2, %index) : (vector<[16]xi1>, vector<[4]xi1>, i32) -> vector<[16]xi1>
// CHECK: call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> %[[PN]], <vscale x 8 x i1> %[[P3]], i32 %[[INDEX]])
"arm_sve.intr.psel"(%pn, %p3, %index) : (vector<[16]xi1>, vector<[8]xi1>, i32) -> vector<[16]xi1>
// CHECK: call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> %[[PN]], <vscale x 16 x i1> %[[P4]], i32 %[[INDEX]])
"arm_sve.intr.psel"(%pn, %p4, %index) : (vector<[16]xi1>, vector<[16]xi1>, i32) -> vector<[16]xi1>
llvm.return
}
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