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[RISCV] Add Syntacore SCR3 processor definition #95953

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Merged
merged 2 commits into from
Jun 21, 2024
Merged

[RISCV] Add Syntacore SCR3 processor definition #95953

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75c4b0d
[RISCV] Add Syntacore SCR3 processor definition
asi-sc Jun 18, 2024
eb4752b
adjust test: one feature - one line
asi-sc Jun 19, 2024
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23 changes: 23 additions & 0 deletions clang/test/Driver/riscv-cpus.c
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Expand Up @@ -358,3 +358,26 @@

// RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
// MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64

// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+m"
// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+c"
// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+zicsr"
// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+zifencei"
// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-abi" "ilp32"

// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr3-rv32 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV32 %s
// MTUNE-SYNTACORE-SCR3-RV32: "-tune-cpu" "syntacore-scr3-rv32"
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I think we don't need to test this, but I don't have a strong opinion here.

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This just copies the checks many processors do (rocket, veyron, xiangshan-nanhu, etc)


// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv64 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV64 %s
// MCPU-SYNTACORE-SCR3-RV64: "-target-cpu" "syntacore-scr3-rv64"
// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+m"
// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+a"
// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+c"
// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+zicsr"
// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+zifencei"
// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-abi" "lp64"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr3-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV64 %s
// MTUNE-SYNTACORE-SCR3-RV64: "-tune-cpu" "syntacore-scr3-rv64"
8 changes: 4 additions & 4 deletions clang/test/Misc/target-invalid-cpu-note.c
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Expand Up @@ -81,16 +81,16 @@

// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
// RISCV32: error: unknown target CPU 'not-a-cpu'
// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}}
// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32{{$}}

// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu{{$}}
// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, veyron-v1, xiangshan-nanhu{{$}}

// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, generic, rocket, sifive-7-series{{$}}

// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.rst
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Expand Up @@ -158,6 +158,7 @@ Changes to the RISC-V Backend
* Zabha is no longer experimental.
* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
* Added smcdeleg, ssccfg, smcsrind, and sscsrind extensions to -march.
* ``-mcpu=syntacore-scr3-rv32`` and ``-mcpu=syntacore-scr3-rv64`` were added.

Changes to the WebAssembly Backend
----------------------------------
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21 changes: 21 additions & 0 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
FeatureStdExtC],
[TuneNoDefaultUnroll]>;

def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",
NoSchedModel,
[Feature32Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
FeatureStdExtZifencei,
FeatureStdExtM,
FeatureStdExtC],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;

def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
NoSchedModel,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
FeatureStdExtZifencei,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtC],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;

def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
NoSchedModel,
[Feature64Bit,
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