Skip to content

AMDGPU/gfx12: Minor documentation update #96079

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jun 19, 2024
Merged

AMDGPU/gfx12: Minor documentation update #96079

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 7 additions & 7 deletions llvm/docs/AMDGPUUsage.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4811,10 +4811,10 @@ The fields used by CP for code objects before V3 also match those specified in
- vgprs_used = align(arch_vgprs, 4)
+ acc_vgprs
- max(0, ceil(vgprs_used / 8) - 1)
GFX10-GFX11 (wavefront size 64)
GFX10-GFX12 (wavefront size 64)
- max_vgpr 1..256
- max(0, ceil(vgprs_used / 4) - 1)
GFX10-GFX11 (wavefront size 32)
GFX10-GFX12 (wavefront size 32)
- max_vgpr 1..256
- max(0, ceil(vgprs_used / 8) - 1)

Expand Down Expand Up @@ -4848,7 +4848,7 @@ The fields used by CP for code objects before V3 also match those specified in
GFX9
- sgprs_used 0..112
- 2 * max(0, ceil(sgprs_used / 16) - 1)
GFX10-GFX11
GFX10-GFX12
Reserved, must be 0.
(128 SGPRs always
allocated.)
Expand Down Expand Up @@ -5028,7 +5028,7 @@ The fields used by CP for code objects before V3 also match those specified in
``COMPUTE_PGM_RSRC1.CDBG_USER``.
26 1 bit FP16_OVFL GFX6-GFX8
Reserved, must be 0.
GFX9-GFX11
GFX9-GFX12
Wavefront starts execution
with specified fp16 overflow
mode.
Expand All @@ -5047,7 +5047,7 @@ The fields used by CP for code objects before V3 also match those specified in
28:27 2 bits Reserved, must be 0.
29 1 bit WGP_MODE GFX6-GFX9
Reserved, must be 0.
GFX10-GFX11
GFX10-GFX12
- If 0 execute work-groups in
CU wavefront execution mode.
- If 1 execute work-groups on
Expand All @@ -5059,7 +5059,7 @@ The fields used by CP for code objects before V3 also match those specified in
``COMPUTE_PGM_RSRC1.WGP_MODE``.
30 1 bit MEM_ORDERED GFX6-GFX9
Reserved, must be 0.
GFX10-GFX11
GFX10-GFX12
Controls the behavior of the
s_waitcnt's vmcnt and vscnt
counters.
Expand All @@ -5082,7 +5082,7 @@ The fields used by CP for code objects before V3 also match those specified in
``COMPUTE_PGM_RSRC1.MEM_ORDERED``.
31 1 bit FWD_PROGRESS GFX6-GFX9
Reserved, must be 0.
GFX10-GFX11
GFX10-GFX12
- If 0 execute SIMD wavefronts
using oldest first policy.
- If 1 execute SIMD wavefronts to
Expand Down
Loading