Skip to content

[llvm][AArch64][TableGen] Create a ProcessorAlias record #96249

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 5 commits into from
Jun 28, 2024
Merged

[llvm][AArch64][TableGen] Create a ProcessorAlias record #96249

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
ee1389a
[llvm][AArch64][TableGen] Create a ProcessorAlias record. NFC
jroelofs Jun 20, 2024
5d2fce1
Revert "[llvm][AArch64][TableGen] Create a ProcessorAlias record. NFC"
jroelofs Jun 21, 2024
7adcf8e
use CpuAlias table instead
jroelofs Jun 21, 2024
a57a46f
define aliases through tablegen
jroelofs Jun 20, 2024
7ea665d
grace is neoverse-v2, not neoverse-n2
jroelofs Jun 28, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion clang/test/Driver/aarch64-mac-cpus.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,4 +21,4 @@
// EXPLICIT-A11: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a11"
// EXPLICIT-A7: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a7"
// EXPLICIT-A14: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a14"
// EXPLICIT-M1: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-m1"
// EXPLICIT-M1: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a14"
4 changes: 2 additions & 2 deletions clang/test/Misc/target-invalid-cpu-note.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,11 +5,11 @@

// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
// AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35, cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-s4, apple-s5, apple-a13, apple-a14, apple-m1, apple-a15, apple-m2, apple-a16, apple-m3, apple-a17, apple-m4, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
// AARCH64-NEXT: note: valid target CPU values are: a64fx, ampere1, ampere1a, ampere1b, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-a7, apple-a8, apple-a9, apple-m1, apple-m2, apple-m3, apple-m4, apple-s4, apple-s5, carmel, cobalt-100, cortex-a34, cortex-a35, cortex-a510, cortex-a520, cortex-a520ae, cortex-a53, cortex-a55, cortex-a57, cortex-a65, cortex-a65ae, cortex-a710, cortex-a715, cortex-a72, cortex-a720, cortex-a720ae, cortex-a725, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, cyclone, exynos-m3, exynos-m4, exynos-m5, falkor, generic, grace, kryo, neoverse-512tvb, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, oryon-1, saphira, thunderx, thunderx2t99, thunderx3t110, thunderxt81, thunderxt83, thunderxt88, tsv110{{$}}
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Split into multiple lines?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Do you mean:

- Diags.Report(diag::note_valid_options) << llvm::join(ValidList, ", ");
+ Diags.Report(diag::note_valid_options) << llvm::join(ValidList, "\n");

or to add a few AARCH64-SAME:'s? The latter seems less preferable, since it leaves holes. For ex. writing:

// AARCH64-NEXT: note: valid target CPU values are: a64fx, ampere1
// AARCH64-SAME: ampere1b, apple-a10

could accidentally miss out on checking for ampere1a, whereas the current form forces complete coverage with the {{$}}.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I meant AARCH64-SAME, but you are right, that will potentially miss things. I'd be happy with changing the actual output format, but it doesn't have to be done in this PR.


// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
// TUNE_AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35, cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88, thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-s4, apple-s5, apple-a13, apple-a14, apple-m1, apple-a15, apple-m2, apple-a16, apple-m3, apple-a17, apple-m4, a64fx, carmel, ampere1, ampere1a, ampere1b, oryon-1, cobalt-100, grace{{$}}
// TUNE_AARCH64-NEXT: note: valid target CPU values are: a64fx, ampere1, ampere1a, ampere1b, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-a7, apple-a8, apple-a9, apple-m1, apple-m2, apple-m3, apple-m4, apple-s4, apple-s5, carmel, cobalt-100, cortex-a34, cortex-a35, cortex-a510, cortex-a520, cortex-a520ae, cortex-a53, cortex-a55, cortex-a57, cortex-a65, cortex-a65ae, cortex-a710, cortex-a715, cortex-a72, cortex-a720, cortex-a720ae, cortex-a725, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, cortex-x925, cyclone, exynos-m3, exynos-m4, exynos-m5, falkor, generic, grace, kryo, neoverse-512tvb, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, oryon-1, saphira, thunderx, thunderx2t99, thunderx3t110, thunderxt81, thunderxt83, thunderxt88, tsv110{{$}}

// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
// X86: error: unknown target CPU 'not-a-cpu'
Expand Down
2 changes: 1 addition & 1 deletion llvm/include/llvm/MC/MCSubtargetInfo.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -225,7 +225,7 @@ class MCSubtargetInfo {
}

/// Check whether the CPU string is valid.
bool isCPUStringValid(StringRef CPU) const {
virtual bool isCPUStringValid(StringRef CPU) const {
auto Found = llvm::lower_bound(ProcDesc, CPU);
return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/include/llvm/TargetParser/AArch64TargetParser.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -304,8 +304,8 @@ struct Alias {
StringRef Name;
};

inline constexpr Alias CpuAliases[] = {{"cobalt-100", "neoverse-n2"},
{"grace", "neoverse-v2"}};
#define EMIT_CPU_ALIAS
#include "llvm/TargetParser/AArch64TargetParserDef.inc"

const ExtensionInfo &getExtensionByID(ArchExtKind(ExtID));

Expand Down
37 changes: 18 additions & 19 deletions llvm/lib/Target/AArch64/AArch64Processors.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -930,6 +930,12 @@ def ProcessorFeatures {
list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
}

// Define an alternative name for a given Processor.
class ProcessorAlias<string n, string alias> {
string Name = n;
string Alias = alias;
}

// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging
// optimizations.
def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic,
Expand Down Expand Up @@ -1005,6 +1011,7 @@ def : ProcessorModel<"neoverse-n1", NeoverseN1Model,
ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>;
def : ProcessorModel<"neoverse-n2", NeoverseN2Model,
ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>;
def : ProcessorAlias<"cobalt-100", "neoverse-n2">;
def : ProcessorModel<"neoverse-n3", NeoverseN2Model,
ProcessorFeatures.NeoverseN3, [TuneNeoverseN3]>;
def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model,
Expand All @@ -1013,6 +1020,7 @@ def : ProcessorModel<"neoverse-v1", NeoverseV1Model,
ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
def : ProcessorModel<"neoverse-v2", NeoverseV2Model,
ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>;
def : ProcessorAlias<"grace", "neoverse-v2">;
def : ProcessorModel<"neoverse-v3", NeoverseV2Model,
ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>;
def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model,
Expand Down Expand Up @@ -1050,15 +1058,12 @@ def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110,

// Apple CPUs

// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7,
[TuneAppleA7]>;
def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7,
[TuneAppleA7]>;
def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7,
[TuneAppleA7]>;
def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7,
[TuneAppleA7]>;
// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
def : ProcessorAlias<"cyclone", "apple-a7">;
def : ProcessorAlias<"apple-a8", "apple-a7">;
def : ProcessorAlias<"apple-a9", "apple-a7">;

def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10,
[TuneAppleA10]>;
Expand All @@ -1068,28 +1073,23 @@ def : ProcessorModel<"apple-a11", CycloneModel, ProcessorFeatures.AppleA11,

def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12,
[TuneAppleA12]>;
def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12,
[TuneAppleA12]>;
def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12,
[TuneAppleA12]>;
def : ProcessorAlias<"apple-s4", "apple-a12">;
def : ProcessorAlias<"apple-s5", "apple-a12">;

def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13,
[TuneAppleA13]>;

def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14,
[TuneAppleA14]>;
def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14,
[TuneAppleA14]>;
def : ProcessorAlias<"apple-m1", "apple-a14">;

def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15,
[TuneAppleA15]>;
def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15,
[TuneAppleA15]>;
def : ProcessorAlias<"apple-m2", "apple-a15">;

def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16,
[TuneAppleA16]>;
def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16,
[TuneAppleA16]>;
def : ProcessorAlias<"apple-m3", "apple-a16">;

def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17,
[TuneAppleA17]>;
Expand All @@ -1098,8 +1098,7 @@ def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4,
[TuneAppleM4]>;

// Alias for the latest Apple processor model supported by LLVM.
def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleM4,
[TuneAppleM4]>;
def : ProcessorAlias<"apple-latest", "apple-m4">;


// Fujitsu A64FX
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Endian.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TargetParser/AArch64TargetParser.h"

using namespace llvm;

Expand All @@ -51,6 +52,8 @@ static MCInstrInfo *createAArch64MCInstrInfo() {

static MCSubtargetInfo *
createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
CPU = AArch64::resolveCPUAlias(CPU);

if (CPU.empty()) {
CPU = "generic";
if (FS.empty())
Expand Down
8 changes: 6 additions & 2 deletions llvm/lib/TargetParser/AArch64TargetParser.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -88,10 +88,14 @@ StringRef AArch64::getArchExtFeature(StringRef ArchExt) {

void AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
for (const auto &C : CpuInfos)
Values.push_back(C.Name);
Values.push_back(C.Name);

for (const auto &Alias : CpuAliases)
Values.push_back(Alias.AltName);
// The apple-latest alias is backend only, do not expose it to clang's -mcpu.
if (Alias.AltName != "apple-latest")
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't love this special case. But, not sure what to do about it.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

apple-latest is a bit of a special snowflake, meant for disassemblers and debuggers. I'm not sure what else to do with it either.

Values.push_back(Alias.AltName);

llvm::sort(Values);
}

bool AArch64::isX18ReservedByDefault(const Triple &TT) {
Expand Down
31 changes: 31 additions & 0 deletions llvm/utils/TableGen/ARMTargetDefEmitter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@

#include "llvm/ADT/StringSet.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/FormatVariadic.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
Expand Down Expand Up @@ -217,6 +218,36 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) {
<< "#endif // EMIT_ARCHITECTURES\n"
<< "\n";

// Emit CPU Aliases
OS << "#ifdef EMIT_CPU_ALIAS\n"
<< "inline constexpr Alias CpuAliases[] = {\n";

llvm::StringSet<> Processors;
for (const Record *Rec : RK.getAllDerivedDefinitions("ProcessorModel"))
Processors.insert(Rec->getValueAsString("Name"));

llvm::StringSet<> Aliases;
for (const Record *Rec : RK.getAllDerivedDefinitions("ProcessorAlias")) {
auto Name = Rec->getValueAsString("Name");
auto Alias = Rec->getValueAsString("Alias");
if (!Processors.contains(Alias))
PrintFatalError(
Rec, "Alias '" + Name + "' references a non-existent ProcessorModel '" + Alias + "'");
if (Processors.contains(Name))
PrintFatalError(
Rec, "Alias '" + Name + "' duplicates an existing ProcessorModel");
if (!Aliases.insert(Name).second)
PrintFatalError(
Rec, "Alias '" + Name + "' duplicates an existing ProcessorAlias");

OS << llvm::formatv(R"( { "{0}", "{1}" },)", Name, Alias) << '\n';
}

OS << "};\n"
<< "#undef EMIT_CPU_ALIAS\n"
<< "#endif // EMIT_CPU_ALIAS\n"
<< "\n";

// Emit CPU information
OS << "#ifdef EMIT_CPU_INFO\n"
<< "inline constexpr CpuInfo CpuInfos[] = {\n";
Expand Down
26 changes: 24 additions & 2 deletions llvm/utils/TableGen/SubtargetEmitter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -239,6 +239,9 @@ void SubtargetEmitter::EmitSubtargetInfoMacroCalls(raw_ostream &OS) {

OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n";

if (Target == "AArch64")
OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
}

//
Expand Down Expand Up @@ -1895,6 +1898,10 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) {
return;
}

if (Target == "AArch64")
OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
<< " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";

OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n"
<< " const FeatureBitset &Bits = getFeatureBits();\n";

Expand Down Expand Up @@ -1946,6 +1953,11 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
"override;\n";
}
if (Target == "AArch64")
OS << " bool isCPUStringValid(StringRef CPU) const override {\n"
<< " CPU = AArch64::resolveCPUAlias(CPU);\n"
<< " return MCSubtargetInfo::isCPUStringValid(CPU);\n"
<< " }\n";
OS << "};\n";
EmitHwModeCheck(Target + "GenMCSubtargetInfo", OS);
}
Expand Down Expand Up @@ -2013,6 +2025,9 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "\nstatic inline MCSubtargetInfo *create" << Target
<< "MCSubtargetInfoImpl("
<< "const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {\n";
if (Target == "AArch64")
OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
<< " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";
OS << " return new " << Target
<< "GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, ";
if (NumFeatures)
Expand Down Expand Up @@ -2045,6 +2060,8 @@ void SubtargetEmitter::run(raw_ostream &OS) {

OS << "#include \"llvm/Support/Debug.h\"\n";
OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";
if (Target == "AArch64")
OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
ParseFeaturesFunction(OS);

OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
Expand Down Expand Up @@ -2112,8 +2129,13 @@ void SubtargetEmitter::run(raw_ostream &OS) {
}

OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
<< "StringRef TuneCPU, StringRef FS)\n"
<< " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
<< "StringRef TuneCPU, StringRef FS)\n";

if (Target == "AArch64")
OS << " : TargetSubtargetInfo(TT, AArch64::resolveCPUAlias(CPU),\n"
<< " AArch64::resolveCPUAlias(TuneCPU), FS, ";
else
OS << " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
if (NumFeatures)
OS << "ArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
else
Expand Down
Loading