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[AMDGPU][NFC] Rename AMDGPUVariadicMCExpr to AMDGPUMCExpr. #96618

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Merged
merged 1 commit into from
Jun 25, 2024
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[AMDGPU][NFC] Rename AMDGPUVariadicMCExpr to AMDGPUMCExpr. #96618

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37 changes: 18 additions & 19 deletions llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -793,7 +793,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
// The calculations related to SGPR/VGPR blocks are
// duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
// unified.
const MCExpr *ExtraSGPRs = AMDGPUVariadicMCExpr::createExtraSGPRs(
const MCExpr *ExtraSGPRs = AMDGPUMCExpr::createExtraSGPRs(
ProgInfo.VCCUsed, ProgInfo.FlatUsed,
getTargetStreamer()->getTargetID()->isXnackOnOrAny(), Ctx);

Expand Down Expand Up @@ -886,27 +886,27 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
}
}
}
ProgInfo.NumSGPR = AMDGPUVariadicMCExpr::createMax(
ProgInfo.NumSGPR = AMDGPUMCExpr::createMax(
{ProgInfo.NumSGPR, CreateExpr(WaveDispatchNumSGPR)}, Ctx);

ProgInfo.NumArchVGPR = AMDGPUVariadicMCExpr::createMax(
ProgInfo.NumArchVGPR = AMDGPUMCExpr::createMax(
{ProgInfo.NumVGPR, CreateExpr(WaveDispatchNumVGPR)}, Ctx);

ProgInfo.NumVGPR = AMDGPUVariadicMCExpr::createTotalNumVGPR(
ProgInfo.NumVGPR = AMDGPUMCExpr::createTotalNumVGPR(
ProgInfo.NumAccVGPR, ProgInfo.NumArchVGPR, Ctx);
}

// Adjust number of registers used to meet default/requested minimum/maximum
// number of waves per execution unit request.
unsigned MaxWaves = MFI->getMaxWavesPerEU();
ProgInfo.NumSGPRsForWavesPerEU = AMDGPUVariadicMCExpr::createMax(
{ProgInfo.NumSGPR, CreateExpr(1ul),
CreateExpr(STM.getMinNumSGPRs(MaxWaves))},
Ctx);
ProgInfo.NumVGPRsForWavesPerEU = AMDGPUVariadicMCExpr::createMax(
{ProgInfo.NumVGPR, CreateExpr(1ul),
CreateExpr(STM.getMinNumVGPRs(MaxWaves))},
Ctx);
ProgInfo.NumSGPRsForWavesPerEU =
AMDGPUMCExpr::createMax({ProgInfo.NumSGPR, CreateExpr(1ul),
CreateExpr(STM.getMinNumSGPRs(MaxWaves))},
Ctx);
ProgInfo.NumVGPRsForWavesPerEU =
AMDGPUMCExpr::createMax({ProgInfo.NumVGPR, CreateExpr(1ul),
CreateExpr(STM.getMinNumVGPRs(MaxWaves))},
Ctx);

if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
STM.hasSGPRInitBug()) {
Expand Down Expand Up @@ -955,10 +955,9 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
unsigned Granule) {
const MCExpr *OneConst = CreateExpr(1ul);
const MCExpr *GranuleConst = CreateExpr(Granule);
const MCExpr *MaxNumGPR =
AMDGPUVariadicMCExpr::createMax({NumGPR, OneConst}, Ctx);
const MCExpr *MaxNumGPR = AMDGPUMCExpr::createMax({NumGPR, OneConst}, Ctx);
const MCExpr *AlignToGPR =
AMDGPUVariadicMCExpr::createAlignTo(MaxNumGPR, GranuleConst, Ctx);
AMDGPUMCExpr::createAlignTo(MaxNumGPR, GranuleConst, Ctx);
const MCExpr *DivGPR =
MCBinaryExpr::createDiv(AlignToGPR, GranuleConst, Ctx);
const MCExpr *SubGPR = MCBinaryExpr::createSub(DivGPR, OneConst, Ctx);
Expand Down Expand Up @@ -1000,7 +999,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
// The MCExpr equivalent of divideCeil.
auto DivideCeil = [&Ctx](const MCExpr *Numerator, const MCExpr *Denominator) {
const MCExpr *Ceil =
AMDGPUVariadicMCExpr::createAlignTo(Numerator, Denominator, Ctx);
AMDGPUMCExpr::createAlignTo(Numerator, Denominator, Ctx);
return MCBinaryExpr::createDiv(Ceil, Denominator, Ctx);
};

Expand Down Expand Up @@ -1073,7 +1072,7 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT);
}

ProgInfo.Occupancy = AMDGPUVariadicMCExpr::createOccupancy(
ProgInfo.Occupancy = AMDGPUMCExpr::createOccupancy(
STM.computeOccupancy(F, ProgInfo.LDSSize), ProgInfo.NumSGPRsForWavesPerEU,
ProgInfo.NumVGPRsForWavesPerEU, STM, Ctx);

Expand Down Expand Up @@ -1265,8 +1264,8 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
// ScratchSize is in bytes, 16 aligned.
MD->setScratchSize(
CC,
AMDGPUVariadicMCExpr::createAlignTo(CurrentProgramInfo.ScratchSize,
MCConstantExpr::create(16, Ctx), Ctx),
AMDGPUMCExpr::createAlignTo(CurrentProgramInfo.ScratchSize,
MCConstantExpr::create(16, Ctx), Ctx),
Ctx);

if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8357,7 +8357,7 @@ void AMDGPUAsmParser::onBeginOfFile() {
/// max(expr, ...)
///
bool AMDGPUAsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
using AGVK = AMDGPUVariadicMCExpr::VariadicKind;
using AGVK = AMDGPUMCExpr::VariantKind;

if (isToken(AsmToken::Identifier)) {
StringRef TokenId = getTokenStr();
Expand Down Expand Up @@ -8387,7 +8387,7 @@ bool AMDGPUAsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
"mismatch of commas in " + Twine(TokenId) + " expression");
return true;
}
Res = AMDGPUVariadicMCExpr::create(VK, Exprs, getContext());
Res = AMDGPUMCExpr::create(VK, Exprs, getContext());
return false;
}
const MCExpr *Expr;
Expand Down
96 changes: 45 additions & 51 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCExpr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21,13 +21,11 @@
using namespace llvm;
using namespace llvm::AMDGPU;

AMDGPUVariadicMCExpr::AMDGPUVariadicMCExpr(VariadicKind Kind,
ArrayRef<const MCExpr *> Args,
MCContext &Ctx)
AMDGPUMCExpr::AMDGPUMCExpr(VariantKind Kind, ArrayRef<const MCExpr *> Args,
MCContext &Ctx)
: Kind(Kind), Ctx(Ctx) {
assert(Args.size() >= 1 && "Needs a minimum of one expression.");
assert(Kind != AGVK_None &&
"Cannot construct AMDGPUVariadicMCExpr of kind none.");
assert(Kind != AGVK_None && "Cannot construct AMDGPUMCExpr of kind none.");

// Allocating the variadic arguments through the same allocation mechanism
// that the object itself is allocated with so they end up in the same memory.
Expand All @@ -40,25 +38,23 @@ AMDGPUVariadicMCExpr::AMDGPUVariadicMCExpr(VariadicKind Kind,
this->Args = ArrayRef<const MCExpr *>(RawArgs, Args.size());
}

AMDGPUVariadicMCExpr::~AMDGPUVariadicMCExpr() { Ctx.deallocate(RawArgs); }
AMDGPUMCExpr::~AMDGPUMCExpr() { Ctx.deallocate(RawArgs); }

const AMDGPUVariadicMCExpr *
AMDGPUVariadicMCExpr::create(VariadicKind Kind, ArrayRef<const MCExpr *> Args,
MCContext &Ctx) {
return new (Ctx) AMDGPUVariadicMCExpr(Kind, Args, Ctx);
const AMDGPUMCExpr *AMDGPUMCExpr::create(VariantKind Kind,
ArrayRef<const MCExpr *> Args,
MCContext &Ctx) {
return new (Ctx) AMDGPUMCExpr(Kind, Args, Ctx);
}

const MCExpr *AMDGPUVariadicMCExpr::getSubExpr(size_t Index) const {
assert(Index < Args.size() &&
"Indexing out of bounds AMDGPUVariadicMCExpr sub-expr");
const MCExpr *AMDGPUMCExpr::getSubExpr(size_t Index) const {
assert(Index < Args.size() && "Indexing out of bounds AMDGPUMCExpr sub-expr");
return Args[Index];
}

void AMDGPUVariadicMCExpr::printImpl(raw_ostream &OS,
const MCAsmInfo *MAI) const {
void AMDGPUMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
switch (Kind) {
default:
llvm_unreachable("Unknown AMDGPUVariadicMCExpr kind.");
llvm_unreachable("Unknown AMDGPUMCExpr kind.");
case AGVK_Or:
OS << "or(";
break;
Expand Down Expand Up @@ -86,21 +82,19 @@ void AMDGPUVariadicMCExpr::printImpl(raw_ostream &OS,
OS << ')';
}

static int64_t op(AMDGPUVariadicMCExpr::VariadicKind Kind, int64_t Arg1,
int64_t Arg2) {
static int64_t op(AMDGPUMCExpr::VariantKind Kind, int64_t Arg1, int64_t Arg2) {
switch (Kind) {
default:
llvm_unreachable("Unknown AMDGPUVariadicMCExpr kind.");
case AMDGPUVariadicMCExpr::AGVK_Max:
llvm_unreachable("Unknown AMDGPUMCExpr kind.");
case AMDGPUMCExpr::AGVK_Max:
return std::max(Arg1, Arg2);
case AMDGPUVariadicMCExpr::AGVK_Or:
case AMDGPUMCExpr::AGVK_Or:
return Arg1 | Arg2;
}
}

bool AMDGPUVariadicMCExpr::evaluateExtraSGPRs(MCValue &Res,
const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
bool AMDGPUMCExpr::evaluateExtraSGPRs(MCValue &Res, const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) {
MCValue MCVal;
if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) ||
Expand All @@ -112,7 +106,7 @@ bool AMDGPUVariadicMCExpr::evaluateExtraSGPRs(MCValue &Res,
};

assert(Args.size() == 3 &&
"AMDGPUVariadic Argument count incorrect for ExtraSGPRs");
"AMDGPUMCExpr Argument count incorrect for ExtraSGPRs");
const MCSubtargetInfo *STI = Ctx.getSubtargetInfo();
uint64_t VCCUsed = 0, FlatScrUsed = 0, XNACKUsed = 0;

Expand All @@ -129,9 +123,8 @@ bool AMDGPUVariadicMCExpr::evaluateExtraSGPRs(MCValue &Res,
return true;
}

bool AMDGPUVariadicMCExpr::evaluateTotalNumVGPR(MCValue &Res,
const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
bool AMDGPUMCExpr::evaluateTotalNumVGPR(MCValue &Res, const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) {
MCValue MCVal;
if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) ||
Expand All @@ -142,7 +135,7 @@ bool AMDGPUVariadicMCExpr::evaluateTotalNumVGPR(MCValue &Res,
return true;
};
assert(Args.size() == 2 &&
"AMDGPUVariadic Argument count incorrect for TotalNumVGPRs");
"AMDGPUMCExpr Argument count incorrect for TotalNumVGPRs");
const MCSubtargetInfo *STI = Ctx.getSubtargetInfo();
uint64_t NumAGPR = 0, NumVGPR = 0;

Expand All @@ -158,9 +151,8 @@ bool AMDGPUVariadicMCExpr::evaluateTotalNumVGPR(MCValue &Res,
return true;
}

bool AMDGPUVariadicMCExpr::evaluateAlignTo(MCValue &Res,
const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
bool AMDGPUMCExpr::evaluateAlignTo(MCValue &Res, const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) {
MCValue MCVal;
if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) ||
Expand All @@ -172,7 +164,7 @@ bool AMDGPUVariadicMCExpr::evaluateAlignTo(MCValue &Res,
};

assert(Args.size() == 2 &&
"AMDGPUVariadic Argument count incorrect for AlignTo");
"AMDGPUMCExpr Argument count incorrect for AlignTo");
uint64_t Value = 0, Align = 0;
if (!TryGetMCExprValue(Args[0], Value) || !TryGetMCExprValue(Args[1], Align))
return false;
Expand All @@ -181,9 +173,8 @@ bool AMDGPUVariadicMCExpr::evaluateAlignTo(MCValue &Res,
return true;
}

bool AMDGPUVariadicMCExpr::evaluateOccupancy(MCValue &Res,
const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
bool AMDGPUMCExpr::evaluateOccupancy(MCValue &Res, const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
auto TryGetMCExprValue = [&](const MCExpr *Arg, uint64_t &ConstantValue) {
MCValue MCVal;
if (!Arg->evaluateAsRelocatable(MCVal, Layout, Fixup) ||
Expand All @@ -194,7 +185,7 @@ bool AMDGPUVariadicMCExpr::evaluateOccupancy(MCValue &Res,
return true;
};
assert(Args.size() == 7 &&
"AMDGPUVariadic Argument count incorrect for Occupancy");
"AMDGPUMCExpr Argument count incorrect for Occupancy");
uint64_t InitOccupancy, MaxWaves, Granule, TargetTotalNumVGPRs, Generation,
NumSGPRs, NumVGPRs;

Expand Down Expand Up @@ -226,8 +217,9 @@ bool AMDGPUVariadicMCExpr::evaluateOccupancy(MCValue &Res,
return true;
}

bool AMDGPUVariadicMCExpr::evaluateAsRelocatableImpl(
MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const {
bool AMDGPUMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout,
const MCFixup *Fixup) const {
std::optional<int64_t> Total;

switch (Kind) {
Expand Down Expand Up @@ -258,12 +250,12 @@ bool AMDGPUVariadicMCExpr::evaluateAsRelocatableImpl(
return true;
}

void AMDGPUVariadicMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
void AMDGPUMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
for (const MCExpr *Arg : Args)
Streamer.visitUsedExpr(*Arg);
}

MCFragment *AMDGPUVariadicMCExpr::findAssociatedFragment() const {
MCFragment *AMDGPUMCExpr::findAssociatedFragment() const {
for (const MCExpr *Arg : Args) {
if (Arg->findAssociatedFragment())
return Arg->findAssociatedFragment();
Expand All @@ -275,18 +267,19 @@ MCFragment *AMDGPUVariadicMCExpr::findAssociatedFragment() const {
/// are unresolvable but needed for further MCExprs). Derived from
/// implementation of IsaInfo::getNumExtraSGPRs in AMDGPUBaseInfo.cpp.
///
const AMDGPUVariadicMCExpr *
AMDGPUVariadicMCExpr::createExtraSGPRs(const MCExpr *VCCUsed,
const MCExpr *FlatScrUsed,
bool XNACKUsed, MCContext &Ctx) {
const AMDGPUMCExpr *AMDGPUMCExpr::createExtraSGPRs(const MCExpr *VCCUsed,
const MCExpr *FlatScrUsed,
bool XNACKUsed,
MCContext &Ctx) {

return create(AGVK_ExtraSGPRs,
{VCCUsed, FlatScrUsed, MCConstantExpr::create(XNACKUsed, Ctx)},
Ctx);
}

const AMDGPUVariadicMCExpr *AMDGPUVariadicMCExpr::createTotalNumVGPR(
const MCExpr *NumAGPR, const MCExpr *NumVGPR, MCContext &Ctx) {
const AMDGPUMCExpr *AMDGPUMCExpr::createTotalNumVGPR(const MCExpr *NumAGPR,
const MCExpr *NumVGPR,
MCContext &Ctx) {
return create(AGVK_TotalNumVGPRs, {NumAGPR, NumVGPR}, Ctx);
}

Expand All @@ -295,10 +288,11 @@ const AMDGPUVariadicMCExpr *AMDGPUVariadicMCExpr::createTotalNumVGPR(
/// Remove dependency on GCNSubtarget and depend only only the necessary values
/// for said occupancy computation. Should match computeOccupancy implementation
/// without passing \p STM on.
const AMDGPUVariadicMCExpr *
AMDGPUVariadicMCExpr::createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs,
const MCExpr *NumVGPRs,
const GCNSubtarget &STM, MCContext &Ctx) {
const AMDGPUMCExpr *AMDGPUMCExpr::createOccupancy(unsigned InitOcc,
const MCExpr *NumSGPRs,
const MCExpr *NumVGPRs,
const GCNSubtarget &STM,
MCContext &Ctx) {
unsigned MaxWaves = IsaInfo::getMaxWavesPerEU(&STM);
unsigned Granule = IsaInfo::getVGPRAllocGranule(&STM);
unsigned TargetTotalNumVGPRs = IsaInfo::getTotalNumVGPRs(&STM);
Expand Down
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